system_stm32f4xx.txt 24.8 KB

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; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\flash\obj\system_stm32f4xx.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\system_stm32f4xx.d --cpu=Cortex-M4.fp --apcs=interwork -O1 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Include -I..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\uCOS-III\uC-CPU -I..\..\uCOS-III\uC-LIB -I..\..\uCOS-III\uCOS-III\Ports -I..\..\uCOS-III\uCOS-III\Source -I..\..\uCOS-III\uC-CPU\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uC-LIB\Ports\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uCOS-III\Ports\ARM-Cortex-M4\Generic\RealView -I..\..\User -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\libapp -I..\..\RL-ARM\Config -I..\..\RL-ARM\Driver -I..\..\RL-ARM\RL-RTX\inc -I..\..\User\bsp\BSP -I..\..\RL-ARM\RL-CAN -I..\..\Libraries\DSP_LIB\Include -I..\..\MODBUS\modbus\rtu -I..\..\MODBUS\BARE\port -I..\..\MODBUS\modbus\include -I..\..\User\bsp\BSP -I..\..\PLC -I..\..\Avoid -I..\..\User\parameter -I..\..\User\LaserMotionCtr -I..\..\User\W5100S -I..\..\User\bsp -I..\..\User\CHASSIS -I..\..\User\CONTROLFUNCTION -I..\..\User\DATAUPDATE -I..\..\User\HARAWARE -I..\..\User\MOTORDRIVER -I..\..\User\NAVAGATION -I..\..\User\PLATFORM -I..\..\User\SENSOR -I.\RTE\_Flash -IC:\Users\YDJ\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include -IC:\Users\YDJ\AppData\Local\Arm\Packs\Keil\STM32F4xx_DFP\2.13.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include -D__UVISION_VERSION=527 -D_RTE_ -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -D__RTX -D__FPU_USED=1 --omf_browse=.\flash\obj\system_stm32f4xx.crf ..\..\User\bsp\system_stm32f4xx.c]
                          THUMB

                          AREA ||i.SetSysClock||, CODE, READONLY, ALIGN=2

                  SetSysClock PROC
;;;563      */
;;;564    static void SetSysClock(void)
000000  b50c              PUSH     {r2,r3,lr}
;;;565    {
;;;566    #if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx)
;;;567    /******************************************************************************/
;;;568    /*            PLL (clocked by HSE) used as System clock source                */
;;;569    /******************************************************************************/
;;;570      __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
000002  2200              MOVS     r2,#0
000004  9201              STR      r2,[sp,#4]
000006  9200              STR      r2,[sp,#0]
;;;571
;;;572      /* Enable HSE */
;;;573      RCC->CR |= ((uint32_t)RCC_CR_HSEON);
000008  4927              LDR      r1,|L1.168|
00000a  6808              LDR      r0,[r1,#0]
00000c  f4403080          ORR      r0,r0,#0x10000
000010  6008              STR      r0,[r1,#0]
;;;574
;;;575      /* Wait till HSE is ready and if Time out is reached exit */
;;;576      do
;;;577      {
;;;578        HSEStatus = RCC->CR & RCC_CR_HSERDY;
;;;579        StartUpCounter++;
;;;580      } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
000012  f44f43a0          MOV      r3,#0x5000
                  |L1.22|
000016  6808              LDR      r0,[r1,#0]            ;578
000018  f4003000          AND      r0,r0,#0x20000        ;578
00001c  9000              STR      r0,[sp,#0]            ;578
00001e  9801              LDR      r0,[sp,#4]            ;579
000020  1c40              ADDS     r0,r0,#1              ;579
000022  9001              STR      r0,[sp,#4]            ;579
000024  9800              LDR      r0,[sp,#0]
000026  b910              CBNZ     r0,|L1.46|
000028  9801              LDR      r0,[sp,#4]
00002a  4298              CMP      r0,r3
00002c  d1f3              BNE      |L1.22|
                  |L1.46|
;;;581
;;;582      if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00002e  6808              LDR      r0,[r1,#0]
000030  0380              LSLS     r0,r0,#14
000032  d502              BPL      |L1.58|
;;;583      {
;;;584        HSEStatus = (uint32_t)0x01;
000034  2001              MOVS     r0,#1
000036  9000              STR      r0,[sp,#0]
000038  e000              B        |L1.60|
                  |L1.58|
;;;585      }
;;;586      else
;;;587      {
;;;588        HSEStatus = (uint32_t)0x00;
00003a  9200              STR      r2,[sp,#0]
                  |L1.60|
;;;589      }
;;;590
;;;591      if (HSEStatus == (uint32_t)0x01)
00003c  9800              LDR      r0,[sp,#0]
00003e  2801              CMP      r0,#1
000040  d131              BNE      |L1.166|
;;;592      {
;;;593        /* Select regulator voltage output Scale 1 mode */
;;;594        RCC->APB1ENR |= RCC_APB1ENR_PWREN;
000042  4819              LDR      r0,|L1.168|
000044  3040              ADDS     r0,r0,#0x40
000046  6802              LDR      r2,[r0,#0]
000048  f0425280          ORR      r2,r2,#0x10000000
00004c  6002              STR      r2,[r0,#0]
;;;595        PWR->CR |= PWR_CR_VOS;
00004e  4817              LDR      r0,|L1.172|
000050  6802              LDR      r2,[r0,#0]
000052  f4424240          ORR      r2,r2,#0xc000
000056  6002              STR      r2,[r0,#0]
;;;596
;;;597        /* HCLK = SYSCLK / 1*/
;;;598        RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
000058  4813              LDR      r0,|L1.168|
00005a  3008              ADDS     r0,r0,#8
00005c  6802              LDR      r2,[r0,#0]
00005e  6002              STR      r2,[r0,#0]
;;;599
;;;600    #if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx)
;;;601        /* PCLK2 = HCLK / 2*/
;;;602        RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
000060  6802              LDR      r2,[r0,#0]
000062  f4424200          ORR      r2,r2,#0x8000
000066  6002              STR      r2,[r0,#0]
;;;603
;;;604        /* PCLK1 = HCLK / 4*/
;;;605        RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
000068  6802              LDR      r2,[r0,#0]
00006a  f44252a0          ORR      r2,r2,#0x1400
00006e  6002              STR      r2,[r0,#0]
;;;606    #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx */
;;;607
;;;608    #if defined (STM32F401xx)
;;;609        /* PCLK2 = HCLK / 2*/
;;;610        RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
;;;611
;;;612        /* PCLK1 = HCLK / 4*/
;;;613        RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
;;;614    #endif /* STM32F401xx */
;;;615
;;;616        /* Configure the main PLL */
;;;617        RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
000070  1f02              SUBS     r2,r0,#4
000072  4b0f              LDR      r3,|L1.176|
000074  6013              STR      r3,[r2,#0]
;;;618                       (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
;;;619
;;;620        /* Enable the main PLL */
;;;621        RCC->CR |= RCC_CR_PLLON;
000076  680a              LDR      r2,[r1,#0]
000078  f0427280          ORR      r2,r2,#0x1000000
00007c  600a              STR      r2,[r1,#0]
                  |L1.126|
;;;622
;;;623        /* Wait till the main PLL is ready */
;;;624        while((RCC->CR & RCC_CR_PLLRDY) == 0)
00007e  680a              LDR      r2,[r1,#0]
000080  0192              LSLS     r2,r2,#6
000082  d5fc              BPL      |L1.126|
;;;625        {
;;;626        }
;;;627
;;;628    #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
;;;629        /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
;;;630        PWR->CR |= PWR_CR_ODEN;
;;;631        while((PWR->CSR & PWR_CSR_ODRDY) == 0)
;;;632        {
;;;633        }
;;;634        PWR->CR |= PWR_CR_ODSWEN;
;;;635        while((PWR->CSR & PWR_CSR_ODSWRDY) == 0)
;;;636        {
;;;637        }
;;;638        /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
;;;639        FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
;;;640    #endif /* STM32F427_437x || STM32F429_439xx  */
;;;641
;;;642    #if defined (STM32F40_41xxx)
;;;643        /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
;;;644        FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
000084  4a0b              LDR      r2,|L1.180|
000086  f2407105          MOV      r1,#0x705
00008a  6011              STR      r1,[r2,#0]
;;;645    #endif /* STM32F40_41xxx  */
;;;646
;;;647    #if defined (STM32F401xx)
;;;648        /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
;;;649        FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
;;;650    #endif /* STM32F401xx */
;;;651
;;;652        /* Select the main PLL as system clock source */
;;;653        RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00008c  6801              LDR      r1,[r0,#0]
00008e  f0210103          BIC      r1,r1,#3
000092  6001              STR      r1,[r0,#0]
;;;654        RCC->CFGR |= RCC_CFGR_SW_PLL;
000094  6801              LDR      r1,[r0,#0]
000096  f0410102          ORR      r1,r1,#2
00009a  6001              STR      r1,[r0,#0]
                  |L1.156|
;;;655
;;;656        /* Wait till the main PLL is used as system clock source */
;;;657        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
00009c  6801              LDR      r1,[r0,#0]
00009e  f3c10181          UBFX     r1,r1,#2,#2
0000a2  2902              CMP      r1,#2
0000a4  d1fa              BNE      |L1.156|
                  |L1.166|
;;;658        {
;;;659        }
;;;660      }
;;;661      else
;;;662      { /* If HSE fails to start-up, the application will have wrong clock
;;;663             configuration. User can add here some code to deal with this error */
;;;664      }
;;;665    #elif defined (STM32F411xE)
;;;666    #if defined (USE_HSE_BYPASS)
;;;667    /******************************************************************************/
;;;668    /*            PLL (clocked by HSE) used as System clock source                */
;;;669    /******************************************************************************/
;;;670      __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
;;;671
;;;672      /* Enable HSE and HSE BYPASS */
;;;673      RCC->CR |= ((uint32_t)RCC_CR_HSEON | RCC_CR_HSEBYP);
;;;674
;;;675      /* Wait till HSE is ready and if Time out is reached exit */
;;;676      do
;;;677      {
;;;678        HSEStatus = RCC->CR & RCC_CR_HSERDY;
;;;679        StartUpCounter++;
;;;680      } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
;;;681
;;;682      if ((RCC->CR & RCC_CR_HSERDY) != RESET)
;;;683      {
;;;684        HSEStatus = (uint32_t)0x01;
;;;685      }
;;;686      else
;;;687      {
;;;688        HSEStatus = (uint32_t)0x00;
;;;689      }
;;;690
;;;691      if (HSEStatus == (uint32_t)0x01)
;;;692      {
;;;693        /* Select regulator voltage output Scale 1 mode */
;;;694        RCC->APB1ENR |= RCC_APB1ENR_PWREN;
;;;695        PWR->CR |= PWR_CR_VOS;
;;;696
;;;697        /* HCLK = SYSCLK / 1*/
;;;698        RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
;;;699
;;;700        /* PCLK2 = HCLK / 2*/
;;;701        RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
;;;702
;;;703        /* PCLK1 = HCLK / 4*/
;;;704        RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
;;;705
;;;706        /* Configure the main PLL */
;;;707        RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
;;;708                       (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
;;;709
;;;710        /* Enable the main PLL */
;;;711        RCC->CR |= RCC_CR_PLLON;
;;;712
;;;713        /* Wait till the main PLL is ready */
;;;714        while((RCC->CR & RCC_CR_PLLRDY) == 0)
;;;715        {
;;;716        }
;;;717
;;;718        /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
;;;719        FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
;;;720
;;;721        /* Select the main PLL as system clock source */
;;;722        RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
;;;723        RCC->CFGR |= RCC_CFGR_SW_PLL;
;;;724
;;;725        /* Wait till the main PLL is used as system clock source */
;;;726        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
;;;727        {
;;;728        }
;;;729      }
;;;730      else
;;;731      { /* If HSE fails to start-up, the application will have wrong clock
;;;732             configuration. User can add here some code to deal with this error */
;;;733      }
;;;734    #else /* HSI will be used as PLL clock source */
;;;735      /* Select regulator voltage output Scale 1 mode */
;;;736      RCC->APB1ENR |= RCC_APB1ENR_PWREN;
;;;737      PWR->CR |= PWR_CR_VOS;
;;;738
;;;739      /* HCLK = SYSCLK / 1*/
;;;740      RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
;;;741
;;;742      /* PCLK2 = HCLK / 2*/
;;;743      RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
;;;744
;;;745      /* PCLK1 = HCLK / 4*/
;;;746      RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
;;;747
;;;748      /* Configure the main PLL */
;;;749      RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (PLL_Q << 24);
;;;750
;;;751      /* Enable the main PLL */
;;;752      RCC->CR |= RCC_CR_PLLON;
;;;753
;;;754      /* Wait till the main PLL is ready */
;;;755      while((RCC->CR & RCC_CR_PLLRDY) == 0)
;;;756      {
;;;757      }
;;;758
;;;759      /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
;;;760      FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
;;;761
;;;762      /* Select the main PLL as system clock source */
;;;763      RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
;;;764      RCC->CFGR |= RCC_CFGR_SW_PLL;
;;;765
;;;766      /* Wait till the main PLL is used as system clock source */
;;;767      while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
;;;768      {
;;;769      }
;;;770    #endif /* USE_HSE_BYPASS */
;;;771    #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx */
;;;772    }
0000a6  bd0c              POP      {r2,r3,pc}
;;;773
                          ENDP

                  |L1.168|
                          DCD      0x40023800
                  |L1.172|
                          DCD      0x40007000
                  |L1.176|
                          DCD      0x07405408
                  |L1.180|
                          DCD      0x40023c00

                          AREA ||i.SystemCoreClockUpdate||, CODE, READONLY, ALIGN=2

                  SystemCoreClockUpdate PROC
;;;493      */
;;;494    void SystemCoreClockUpdate(void)
000000  b570              PUSH     {r4-r6,lr}
;;;495    {
;;;496      uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
;;;497
;;;498      /* Get SYSCLK source -------------------------------------------------------*/
;;;499      tmp = RCC->CFGR & RCC_CFGR_SWS;
000002  4e1d              LDR      r6,|L2.120|
000004  6830              LDR      r0,[r6,#0]
000006  f000000c          AND      r0,r0,#0xc
;;;500
;;;501      switch (tmp)
;;;502      {
;;;503        case 0x00:  /* HSI used as system clock source */
;;;504          SystemCoreClock = HSI_VALUE;
00000a  4b1c              LDR      r3,|L2.124|
00000c  491c              LDR      r1,|L2.128|
00000e  2800              CMP      r0,#0                 ;501
000010  d00f              BEQ      |L2.50|
;;;505          break;
;;;506        case 0x04:  /* HSE used as system clock source */
;;;507          SystemCoreClock = HSE_VALUE;
000012  105d              ASRS     r5,r3,#1
000014  2804              CMP      r0,#4                 ;501
000016  d00e              BEQ      |L2.54|
000018  2808              CMP      r0,#8                 ;501
00001a  d00e              BEQ      |L2.58|
;;;508          break;
;;;509        case 0x08:  /* PLL used as system clock source */
;;;510           /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
;;;511             SYSCLK = PLL_VCO / PLL_P
;;;512             */
;;;513          pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
;;;514          pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
;;;515
;;;516    #if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx)
;;;517          if (pllsource != 0)
;;;518          {
;;;519            /* HSE used as PLL clock source */
;;;520            pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
;;;521          }
;;;522          else
;;;523          {
;;;524            /* HSI used as PLL clock source */
;;;525            pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
;;;526          }
;;;527    #elif defined (STM32F411xE)
;;;528    #if defined (USE_HSE_BYPASS)
;;;529          if (pllsource != 0)
;;;530          {
;;;531            /* HSE used as PLL clock source */
;;;532            pllvco = (HSE_BYPASS_INPUT_FREQUENCY / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
;;;533          }
;;;534    #else
;;;535          if (pllsource == 0)
;;;536          {
;;;537            /* HSI used as PLL clock source */
;;;538            pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
;;;539          }
;;;540    #endif /* USE_HSE_BYPASS */
;;;541    #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx */
;;;542          pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
;;;543          SystemCoreClock = pllvco/pllp;
;;;544          break;
;;;545        default:
;;;546          SystemCoreClock = HSI_VALUE;
00001c  600b              STR      r3,[r1,#0]  ; SystemCoreClock
                  |L2.30|
;;;547          break;
;;;548      }
;;;549      /* Compute HCLK frequency --------------------------------------------------*/
;;;550      /* Get HCLK prescaler */
;;;551      tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00001e  6830              LDR      r0,[r6,#0]
000020  4a17              LDR      r2,|L2.128|
000022  f3c01003          UBFX     r0,r0,#4,#4
000026  1d12              ADDS     r2,r2,#4
000028  5c10              LDRB     r0,[r2,r0]
;;;552      /* HCLK frequency */
;;;553      SystemCoreClock >>= tmp;
00002a  680a              LDR      r2,[r1,#0]  ; SystemCoreClock
00002c  40c2              LSRS     r2,r2,r0
00002e  600a              STR      r2,[r1,#0]  ; SystemCoreClock
000030  bd70              POP      {r4-r6,pc}            ;505
                  |L2.50|
000032  600b              STR      r3,[r1,#0]            ;504  ; SystemCoreClock
000034  e7f3              B        |L2.30|
                  |L2.54|
000036  600d              STR      r5,[r1,#0]            ;507  ; SystemCoreClock
000038  e7f1              B        |L2.30|
                  |L2.58|
00003a  4a0f              LDR      r2,|L2.120|
00003c  1f12              SUBS     r2,r2,#4              ;513
00003e  6810              LDR      r0,[r2,#0]            ;513
000040  f3c05480          UBFX     r4,r0,#22,#1          ;513
000044  6810              LDR      r0,[r2,#0]            ;514
000046  f000003f          AND      r0,r0,#0x3f           ;514
00004a  b134              CBZ      r4,|L2.90|
00004c  fbb5f0f0          UDIV     r0,r5,r0              ;520
000050  6813              LDR      r3,[r2,#0]            ;520
000052  f3c31388          UBFX     r3,r3,#6,#9           ;520
000056  4358              MULS     r0,r3,r0              ;520
000058  e005              B        |L2.102|
                  |L2.90|
00005a  fbb3f0f0          UDIV     r0,r3,r0              ;525
00005e  6813              LDR      r3,[r2,#0]            ;525
000060  f3c31388          UBFX     r3,r3,#6,#9           ;525
000064  4358              MULS     r0,r3,r0              ;525
                  |L2.102|
000066  6812              LDR      r2,[r2,#0]            ;542
000068  f3c24201          UBFX     r2,r2,#16,#2          ;542
00006c  1c52              ADDS     r2,r2,#1              ;542
00006e  0052              LSLS     r2,r2,#1              ;542
000070  fbb0f0f2          UDIV     r0,r0,r2              ;543
000074  6008              STR      r0,[r1,#0]            ;543  ; SystemCoreClock
000076  e7d2              B        |L2.30|
;;;554    }
;;;555
                          ENDP

                  |L2.120|
                          DCD      0x40023808
                  |L2.124|
                          DCD      0x00f42400
                  |L2.128|
                          DCD      ||.data||

                          AREA ||i.SystemInit||, CODE, READONLY, ALIGN=2

                  SystemInit PROC
;;;416      */
;;;417    void SystemInit(void)
000000  b510              PUSH     {r4,lr}
;;;418    {
;;;419      /* FPU settings ------------------------------------------------------------*/
;;;420      #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
;;;421        SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
000002  4812              LDR      r0,|L3.76|
000004  6801              LDR      r1,[r0,#0]
000006  f4410170          ORR      r1,r1,#0xf00000
00000a  6001              STR      r1,[r0,#0]
;;;422      #endif
;;;423      /* Reset the RCC clock configuration to the default reset state ------------*/
;;;424      /* Set HSION bit */
;;;425      RCC->CR |= (uint32_t)0x00000001;
00000c  4810              LDR      r0,|L3.80|
00000e  6801              LDR      r1,[r0,#0]
000010  f0410101          ORR      r1,r1,#1
000014  6001              STR      r1,[r0,#0]
;;;426
;;;427      /* Reset CFGR register */
;;;428      RCC->CFGR = 0x00000000;
000016  4a0e              LDR      r2,|L3.80|
000018  2100              MOVS     r1,#0
00001a  3208              ADDS     r2,r2,#8
00001c  6011              STR      r1,[r2,#0]
;;;429
;;;430      /* Reset HSEON, CSSON and PLLON bits */
;;;431      RCC->CR &= (uint32_t)0xFEF6FFFF;
00001e  6802              LDR      r2,[r0,#0]
000020  4b0c              LDR      r3,|L3.84|
000022  401a              ANDS     r2,r2,r3
000024  6002              STR      r2,[r0,#0]
;;;432
;;;433      /* Reset PLLCFGR register */
;;;434      RCC->PLLCFGR = 0x24003010;
000026  1d03              ADDS     r3,r0,#4
000028  4a0b              LDR      r2,|L3.88|
00002a  601a              STR      r2,[r3,#0]
;;;435
;;;436      /* Reset HSEBYP bit */
;;;437      RCC->CR &= (uint32_t)0xFFFBFFFF;
00002c  6802              LDR      r2,[r0,#0]
00002e  f4222280          BIC      r2,r2,#0x40000
000032  6002              STR      r2,[r0,#0]
;;;438
;;;439      /* Disable all interrupts */
;;;440      RCC->CIR = 0x00000000;
000034  4806              LDR      r0,|L3.80|
000036  300c              ADDS     r0,r0,#0xc
000038  6001              STR      r1,[r0,#0]
;;;441
;;;442    #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
;;;443      SystemInit_ExtMemCtl();
;;;444    #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
;;;445
;;;446      /* Configure the System clock source, PLL Multiplier and Divider factors,
;;;447         AHB/APBx prescalers and Flash settings ----------------------------------*/
;;;448      SetSysClock();
00003a  f7fffffe          BL       SetSysClock
;;;449
;;;450      /* Configure the Vector Table location add offset address ------------------*/
;;;451    #ifdef VECT_TAB_SRAM
;;;452      SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
;;;453    #else
;;;454      SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
00003e  4903              LDR      r1,|L3.76|
000040  f04f6000          MOV      r0,#0x8000000
000044  3980              SUBS     r1,r1,#0x80
000046  6008              STR      r0,[r1,#0]
;;;455    #endif
;;;456    }
000048  bd10              POP      {r4,pc}
;;;457
                          ENDP

00004a  0000              DCW      0x0000
                  |L3.76|
                          DCD      0xe000ed88
                  |L3.80|
                          DCD      0x40023800
                  |L3.84|
                          DCD      0xfef6ffff
                  |L3.88|
                          DCD      0x24003010

                          AREA ||.data||, DATA, ALIGN=2

                  SystemCoreClock
                          DCD      0x0a037a00
                  AHBPrescTable
000004  00000000          DCB      0x00,0x00,0x00,0x00
000008  00000000          DCB      0x00,0x00,0x00,0x00
00000c  01020304          DCB      0x01,0x02,0x03,0x04
000010  06070809          DCB      0x06,0x07,0x08,0x09

;*** Start embedded assembler ***

#line 1 "..\\..\\User\\bsp\\system_stm32f4xx.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___18_system_stm32f4xx_c_5d646a67____REV16|
#line 129 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h"
|__asm___18_system_stm32f4xx_c_5d646a67____REV16| PROC
#line 130

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___18_system_stm32f4xx_c_5d646a67____REVSH|
#line 144
|__asm___18_system_stm32f4xx_c_5d646a67____REVSH| PROC
#line 145

 revsh r0, r0
 bx lr
	ENDP
	AREA ||.rrx_text||, CODE
	THUMB
	EXPORT |__asm___18_system_stm32f4xx_c_5d646a67____RRX|
#line 300
|__asm___18_system_stm32f4xx_c_5d646a67____RRX| PROC
#line 301

 rrx r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***