AGV / agv_shengyiPPxiaoche · Files

; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\flash\obj\stm32f4xx_tim.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\stm32f4xx_tim.d --cpu=Cortex-M4.fp --apcs=interwork -O1 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Include -I..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\uCOS-III\uC-CPU -I..\..\uCOS-III\uC-LIB -I..\..\uCOS-III\uCOS-III\Ports -I..\..\uCOS-III\uCOS-III\Source -I..\..\uCOS-III\uC-CPU\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uC-LIB\Ports\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uCOS-III\Ports\ARM-Cortex-M4\Generic\RealView -I..\..\User -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\libapp -I..\..\RL-ARM\Config -I..\..\RL-ARM\Driver -I..\..\RL-ARM\RL-RTX\inc -I..\..\User\bsp\BSP -I..\..\RL-ARM\RL-CAN -I..\..\Libraries\DSP_LIB\Include -I..\..\MODBUS\modbus\rtu -I..\..\MODBUS\BARE\port -I..\..\MODBUS\modbus\include -I..\..\User\bsp\BSP -I..\..\PLC -I..\..\Avoid -I..\..\User\parameter -I..\..\User\LaserMotionCtr -I..\..\User\W5100S -I..\..\User\bsp -I..\..\User\CHASSIS -I..\..\User\CONTROLFUNCTION -I..\..\User\DATAUPDATE -I..\..\User\HARAWARE -I..\..\User\MOTORDRIVER -I..\..\User\NAVAGATION -I..\..\User\PLATFORM -I..\..\User\SENSOR -I.\RTE\_Flash -IC:\Users\YDJ\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include -IC:\Users\YDJ\AppData\Local\Arm\Packs\Keil\STM32F4xx_DFP\2.13.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include -D__UVISION_VERSION=527 -D_RTE_ -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -D__RTX -D__FPU_USED=1 --omf_browse=.\flash\obj\stm32f4xx_tim.crf ..\..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_tim.c]
                          THUMB

                          AREA ||i.TI1_Config||, CODE, READONLY, ALIGN=1

                  TI1_Config PROC
;;;3203     */
;;;3204   static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
000000  b570              PUSH     {r4-r6,lr}
;;;3205                          uint16_t TIM_ICFilter)
;;;3206   {
;;;3207     uint16_t tmpccmr1 = 0, tmpccer = 0;
;;;3208   
;;;3209     /* Disable the Channel 1: Reset the CC1E Bit */
;;;3210     TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
000002  8c04              LDRH     r4,[r0,#0x20]
000004  f0240401          BIC      r4,r4,#1
000008  8404              STRH     r4,[r0,#0x20]
;;;3211     tmpccmr1 = TIMx->CCMR1;
00000a  8b05              LDRH     r5,[r0,#0x18]
;;;3212     tmpccer = TIMx->CCER;
00000c  8c04              LDRH     r4,[r0,#0x20]
;;;3213   
;;;3214     /* Select the Input and set the filter */
;;;3215     tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F);
00000e  f02505f3          BIC      r5,r5,#0xf3
;;;3216     tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
000012  f64f76ff          MOV      r6,#0xffff
000016  ea061303          AND      r3,r6,r3,LSL #4
00001a  4313              ORRS     r3,r3,r2
00001c  432b              ORRS     r3,r3,r5
;;;3217   
;;;3218     /* Select the Polarity and set the CC1E Bit */
;;;3219     tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
00001e  f024020a          BIC      r2,r4,#0xa
;;;3220     tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
000022  430a              ORRS     r2,r2,r1
000024  f0420101          ORR      r1,r2,#1
;;;3221   
;;;3222     /* Write to TIMx CCMR1 and CCER registers */
;;;3223     TIMx->CCMR1 = tmpccmr1;
000028  8303              STRH     r3,[r0,#0x18]
;;;3224     TIMx->CCER = tmpccer;
00002a  8401              STRH     r1,[r0,#0x20]
;;;3225   }
00002c  bd70              POP      {r4-r6,pc}
;;;3226   
                          ENDP


                          AREA ||i.TI2_Config||, CODE, READONLY, ALIGN=1

                  TI2_Config PROC
;;;3244     */
;;;3245   static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
000000  b570              PUSH     {r4-r6,lr}
;;;3246                          uint16_t TIM_ICFilter)
;;;3247   {
;;;3248     uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
;;;3249   
;;;3250     /* Disable the Channel 2: Reset the CC2E Bit */
;;;3251     TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
000002  8c04              LDRH     r4,[r0,#0x20]
000004  f0240410          BIC      r4,r4,#0x10
000008  8404              STRH     r4,[r0,#0x20]
;;;3252     tmpccmr1 = TIMx->CCMR1;
00000a  8b05              LDRH     r5,[r0,#0x18]
;;;3253     tmpccer = TIMx->CCER;
00000c  8c06              LDRH     r6,[r0,#0x20]
;;;3254     tmp = (uint16_t)(TIM_ICPolarity << 4);
00000e  f64f74ff          MOV      r4,#0xffff
000012  ea041101          AND      r1,r4,r1,LSL #4
;;;3255   
;;;3256     /* Select the Input and set the filter */
;;;3257     tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
000016  f4254573          BIC      r5,r5,#0xf300
;;;3258     tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
00001a  ea043303          AND      r3,r4,r3,LSL #12
00001e  432b              ORRS     r3,r3,r5
;;;3259     tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
000020  ea042202          AND      r2,r4,r2,LSL #8
000024  431a              ORRS     r2,r2,r3
;;;3260   
;;;3261     /* Select the Polarity and set the CC2E Bit */
;;;3262     tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
000026  f02603a0          BIC      r3,r6,#0xa0
;;;3263     tmpccer |=  (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
00002a  430b              ORRS     r3,r3,r1
00002c  f0430110          ORR      r1,r3,#0x10
;;;3264   
;;;3265     /* Write to TIMx CCMR1 and CCER registers */
;;;3266     TIMx->CCMR1 = tmpccmr1 ;
000030  8302              STRH     r2,[r0,#0x18]
;;;3267     TIMx->CCER = tmpccer;
000032  8401              STRH     r1,[r0,#0x20]
;;;3268   }
000034  bd70              POP      {r4-r6,pc}
;;;3269   
                          ENDP


                          AREA ||i.TI3_Config||, CODE, READONLY, ALIGN=1

                  TI3_Config PROC
;;;3286     */
;;;3287   static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
000000  b5f0              PUSH     {r4-r7,lr}
;;;3288                          uint16_t TIM_ICFilter)
;;;3289   {
;;;3290     uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
;;;3291   
;;;3292     /* Disable the Channel 3: Reset the CC3E Bit */
;;;3293     TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
000002  8c04              LDRH     r4,[r0,#0x20]
000004  f4247480          BIC      r4,r4,#0x100
000008  8404              STRH     r4,[r0,#0x20]
;;;3294     tmpccmr2 = TIMx->CCMR2;
00000a  8b86              LDRH     r6,[r0,#0x1c]
;;;3295     tmpccer = TIMx->CCER;
00000c  8c05              LDRH     r5,[r0,#0x20]
;;;3296     tmp = (uint16_t)(TIM_ICPolarity << 8);
00000e  f64f77ff          MOV      r7,#0xffff
000012  ea072401          AND      r4,r7,r1,LSL #8
;;;3297   
;;;3298     /* Select the Input and set the filter */
;;;3299     tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F);
000016  f02606f3          BIC      r6,r6,#0xf3
;;;3300     tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
00001a  ea071103          AND      r1,r7,r3,LSL #4
00001e  4311              ORRS     r1,r1,r2
000020  4331              ORRS     r1,r1,r6
;;;3301   
;;;3302     /* Select the Polarity and set the CC3E Bit */
;;;3303     tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
000022  f4256220          BIC      r2,r5,#0xa00
;;;3304     tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
000026  4322              ORRS     r2,r2,r4
000028  f4427280          ORR      r2,r2,#0x100
;;;3305   
;;;3306     /* Write to TIMx CCMR2 and CCER registers */
;;;3307     TIMx->CCMR2 = tmpccmr2;
00002c  8381              STRH     r1,[r0,#0x1c]
;;;3308     TIMx->CCER = tmpccer;
00002e  8402              STRH     r2,[r0,#0x20]
;;;3309   }
000030  bdf0              POP      {r4-r7,pc}
;;;3310   
                          ENDP


                          AREA ||i.TI4_Config||, CODE, READONLY, ALIGN=1

                  TI4_Config PROC
;;;3327     */
;;;3328   static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
000000  b570              PUSH     {r4-r6,lr}
;;;3329                          uint16_t TIM_ICFilter)
;;;3330   {
;;;3331     uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
;;;3332   
;;;3333     /* Disable the Channel 4: Reset the CC4E Bit */
;;;3334     TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
000002  8c04              LDRH     r4,[r0,#0x20]
000004  f4245480          BIC      r4,r4,#0x1000
000008  8404              STRH     r4,[r0,#0x20]
;;;3335     tmpccmr2 = TIMx->CCMR2;
00000a  8b85              LDRH     r5,[r0,#0x1c]
;;;3336     tmpccer = TIMx->CCER;
00000c  8c06              LDRH     r6,[r0,#0x20]
;;;3337     tmp = (uint16_t)(TIM_ICPolarity << 12);
00000e  f64f74ff          MOV      r4,#0xffff
000012  ea043101          AND      r1,r4,r1,LSL #12
;;;3338   
;;;3339     /* Select the Input and set the filter */
;;;3340     tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
000016  f4254573          BIC      r5,r5,#0xf300
;;;3341     tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
00001a  ea042202          AND      r2,r4,r2,LSL #8
00001e  432a              ORRS     r2,r2,r5
;;;3342     tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
000020  ea043303          AND      r3,r4,r3,LSL #12
000024  4313              ORRS     r3,r3,r2
;;;3343   
;;;3344     /* Select the Polarity and set the CC4E Bit */
;;;3345     tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
000026  f4264220          BIC      r2,r6,#0xa000
;;;3346     tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
00002a  430a              ORRS     r2,r2,r1
00002c  f4425180          ORR      r1,r2,#0x1000
;;;3347   
;;;3348     /* Write to TIMx CCMR2 and CCER registers */
;;;3349     TIMx->CCMR2 = tmpccmr2;
000030  8383              STRH     r3,[r0,#0x1c]
;;;3350     TIMx->CCER = tmpccer ;
000032  8401              STRH     r1,[r0,#0x20]
;;;3351   }
000034  bd70              POP      {r4-r6,pc}
;;;3352   
                          ENDP


                          AREA ||i.TIM_ARRPreloadConfig||, CODE, READONLY, ALIGN=1

                  TIM_ARRPreloadConfig PROC
;;;521      */
;;;522    void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;523    {
000002  d004              BEQ      |L5.14|
;;;524      /* Check the parameters */
;;;525      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;526      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;527    
;;;528      if (NewState != DISABLE)
;;;529      {
;;;530        /* Set the ARR Preload Bit */
;;;531        TIMx->CR1 |= TIM_CR1_ARPE;
000004  8801              LDRH     r1,[r0,#0]
000006  f0410180          ORR      r1,r1,#0x80
00000a  8001              STRH     r1,[r0,#0]
;;;532      }
;;;533      else
;;;534      {
;;;535        /* Reset the ARR Preload Bit */
;;;536        TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE;
;;;537      }
;;;538    }
00000c  4770              BX       lr
                  |L5.14|
00000e  8801              LDRH     r1,[r0,#0]            ;536
000010  f0210180          BIC      r1,r1,#0x80           ;536
000014  8001              STRH     r1,[r0,#0]            ;536
000016  4770              BX       lr
;;;539    
                          ENDP


                          AREA ||i.TIM_BDTRConfig||, CODE, READONLY, ALIGN=1

                  TIM_BDTRConfig PROC
;;;2220     */
;;;2221   void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
000000  b510              PUSH     {r4,lr}
;;;2222   {
;;;2223     /* Check the parameters */
;;;2224     assert_param(IS_TIM_LIST4_PERIPH(TIMx));
;;;2225     assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
;;;2226     assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
;;;2227     assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
;;;2228     assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
;;;2229     assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
;;;2230     assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
;;;2231   
;;;2232     /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
;;;2233        the OSSI State, the dead time value and the Automatic Output Enable Bit */
;;;2234     TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
000002  880a              LDRH     r2,[r1,#0]
000004  884b              LDRH     r3,[r1,#2]
000006  88cc              LDRH     r4,[r1,#6]
000008  431a              ORRS     r2,r2,r3
00000a  888b              LDRH     r3,[r1,#4]
00000c  4323              ORRS     r3,r3,r4
00000e  431a              ORRS     r2,r2,r3
000010  890b              LDRH     r3,[r1,#8]
000012  431a              ORRS     r2,r2,r3
000014  894b              LDRH     r3,[r1,#0xa]
000016  8989              LDRH     r1,[r1,#0xc]
000018  431a              ORRS     r2,r2,r3
00001a  430a              ORRS     r2,r2,r1
00001c  f8a02044          STRH     r2,[r0,#0x44]
;;;2235                TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
;;;2236                TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
;;;2237                TIM_BDTRInitStruct->TIM_AutomaticOutput;
;;;2238   }
000020  bd10              POP      {r4,pc}
;;;2239   
                          ENDP


                          AREA ||i.TIM_BDTRStructInit||, CODE, READONLY, ALIGN=1

                  TIM_BDTRStructInit PROC
;;;2245     */
;;;2246   void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
000000  2100              MOVS     r1,#0
;;;2247   {
;;;2248     /* Set the default configuration */
;;;2249     TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
000002  8001              STRH     r1,[r0,#0]
;;;2250     TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
000004  8041              STRH     r1,[r0,#2]
;;;2251     TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
000006  8081              STRH     r1,[r0,#4]
;;;2252     TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
000008  80c1              STRH     r1,[r0,#6]
;;;2253     TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
00000a  8101              STRH     r1,[r0,#8]
;;;2254     TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
00000c  8141              STRH     r1,[r0,#0xa]
;;;2255     TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
00000e  8181              STRH     r1,[r0,#0xc]
;;;2256   }
000010  4770              BX       lr
;;;2257   
                          ENDP


                          AREA ||i.TIM_CCPreloadControl||, CODE, READONLY, ALIGN=1

                  TIM_CCPreloadControl PROC
;;;2314     */
;;;2315   void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;2316   { 
000002  d004              BEQ      |L8.14|
;;;2317     /* Check the parameters */
;;;2318     assert_param(IS_TIM_LIST4_PERIPH(TIMx));
;;;2319     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2320     if (NewState != DISABLE)
;;;2321     {
;;;2322       /* Set the CCPC Bit */
;;;2323       TIMx->CR2 |= TIM_CR2_CCPC;
000004  8881              LDRH     r1,[r0,#4]
000006  f0410101          ORR      r1,r1,#1
00000a  8081              STRH     r1,[r0,#4]
;;;2324     }
;;;2325     else
;;;2326     {
;;;2327       /* Reset the CCPC Bit */
;;;2328       TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC;
;;;2329     }
;;;2330   }
00000c  4770              BX       lr
                  |L8.14|
00000e  8881              LDRH     r1,[r0,#4]            ;2328
000010  f0210101          BIC      r1,r1,#1              ;2328
000014  8081              STRH     r1,[r0,#4]            ;2328
000016  4770              BX       lr
;;;2331   /**
                          ENDP


                          AREA ||i.TIM_CCxCmd||, CODE, READONLY, ALIGN=1

                  TIM_CCxCmd PROC
;;;1785     */
;;;1786   void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
000000  b510              PUSH     {r4,lr}
;;;1787   {
;;;1788     uint16_t tmp = 0;
;;;1789   
;;;1790     /* Check the parameters */
;;;1791     assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 
;;;1792     assert_param(IS_TIM_CHANNEL(TIM_Channel));
;;;1793     assert_param(IS_TIM_CCX(TIM_CCx));
;;;1794   
;;;1795     tmp = CCER_CCE_SET << TIM_Channel;
000002  2301              MOVS     r3,#1
000004  408b              LSLS     r3,r3,r1
;;;1796   
;;;1797     /* Reset the CCxE Bit */
;;;1798     TIMx->CCER &= (uint16_t)~ tmp;
000006  8c04              LDRH     r4,[r0,#0x20]
000008  439c              BICS     r4,r4,r3
00000a  8404              STRH     r4,[r0,#0x20]
;;;1799   
;;;1800     /* Set or reset the CCxE Bit */ 
;;;1801     TIMx->CCER |=  (uint16_t)(TIM_CCx << TIM_Channel);
00000c  8c03              LDRH     r3,[r0,#0x20]
00000e  408a              LSLS     r2,r2,r1
000010  4313              ORRS     r3,r3,r2
000012  8403              STRH     r3,[r0,#0x20]
;;;1802   }
000014  bd10              POP      {r4,pc}
;;;1803   
                          ENDP


                          AREA ||i.TIM_CCxNCmd||, CODE, READONLY, ALIGN=1

                  TIM_CCxNCmd PROC
;;;1815     */
;;;1816   void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
000000  b510              PUSH     {r4,lr}
;;;1817   {
;;;1818     uint16_t tmp = 0;
;;;1819   
;;;1820     /* Check the parameters */
;;;1821     assert_param(IS_TIM_LIST4_PERIPH(TIMx));
;;;1822     assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
;;;1823     assert_param(IS_TIM_CCXN(TIM_CCxN));
;;;1824   
;;;1825     tmp = CCER_CCNE_SET << TIM_Channel;
000002  2304              MOVS     r3,#4
000004  408b              LSLS     r3,r3,r1
;;;1826   
;;;1827     /* Reset the CCxNE Bit */
;;;1828     TIMx->CCER &= (uint16_t) ~tmp;
000006  8c04              LDRH     r4,[r0,#0x20]
000008  439c              BICS     r4,r4,r3
00000a  8404              STRH     r4,[r0,#0x20]
;;;1829   
;;;1830     /* Set or reset the CCxNE Bit */ 
;;;1831     TIMx->CCER |=  (uint16_t)(TIM_CCxN << TIM_Channel);
00000c  8c03              LDRH     r3,[r0,#0x20]
00000e  408a              LSLS     r2,r2,r1
000010  4313              ORRS     r3,r3,r2
000012  8403              STRH     r3,[r0,#0x20]
;;;1832   }
000014  bd10              POP      {r4,pc}
;;;1833   /**
                          ENDP


                          AREA ||i.TIM_ClearFlag||, CODE, READONLY, ALIGN=1

                  TIM_ClearFlag PROC
;;;2484     */
;;;2485   void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
000000  43c9              MVNS     r1,r1
;;;2486   {  
;;;2487     /* Check the parameters */
;;;2488     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2489      
;;;2490     /* Clear the flags */
;;;2491     TIMx->SR = (uint16_t)~TIM_FLAG;
000002  8201              STRH     r1,[r0,#0x10]
;;;2492   }
000004  4770              BX       lr
;;;2493   
                          ENDP


                          AREA ||i.TIM_ClearITPendingBit||, CODE, READONLY, ALIGN=1

                  TIM_ClearITPendingBit PROC
;;;2553     */
;;;2554   void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
000000  43c9              MVNS     r1,r1
;;;2555   {
;;;2556     /* Check the parameters */
;;;2557     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2558   
;;;2559     /* Clear the IT pending Bit */
;;;2560     TIMx->SR = (uint16_t)~TIM_IT;
000002  8201              STRH     r1,[r0,#0x10]
;;;2561   }
000004  4770              BX       lr
;;;2562   
                          ENDP


                          AREA ||i.TIM_ClearOC1Ref||, CODE, READONLY, ALIGN=1

                  TIM_ClearOC1Ref PROC
;;;1475     */
;;;1476   void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
000000  8b02              LDRH     r2,[r0,#0x18]
;;;1477   {
;;;1478     uint16_t tmpccmr1 = 0;
;;;1479   
;;;1480     /* Check the parameters */
;;;1481     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;1482     assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
;;;1483   
;;;1484     tmpccmr1 = TIMx->CCMR1;
;;;1485   
;;;1486     /* Reset the OC1CE Bit */
;;;1487     tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE;
000002  f0220280          BIC      r2,r2,#0x80
;;;1488   
;;;1489     /* Enable or Disable the Output Compare Clear Bit */
;;;1490     tmpccmr1 |= TIM_OCClear;
000006  430a              ORRS     r2,r2,r1
;;;1491   
;;;1492     /* Write to TIMx CCMR1 register */
;;;1493     TIMx->CCMR1 = tmpccmr1;
000008  8302              STRH     r2,[r0,#0x18]
;;;1494   }
00000a  4770              BX       lr
;;;1495   
                          ENDP


                          AREA ||i.TIM_ClearOC2Ref||, CODE, READONLY, ALIGN=1

                  TIM_ClearOC2Ref PROC
;;;1505     */
;;;1506   void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
000000  8b02              LDRH     r2,[r0,#0x18]
;;;1507   {
;;;1508     uint16_t tmpccmr1 = 0;
;;;1509   
;;;1510     /* Check the parameters */
;;;1511     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;1512     assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
;;;1513   
;;;1514     tmpccmr1 = TIMx->CCMR1;
;;;1515   
;;;1516     /* Reset the OC2CE Bit */
;;;1517     tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE;
000002  f3c2020e          UBFX     r2,r2,#0,#15
;;;1518   
;;;1519     /* Enable or Disable the Output Compare Clear Bit */
;;;1520     tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
000006  f64f73ff          MOV      r3,#0xffff
00000a  ea032101          AND      r1,r3,r1,LSL #8
00000e  4311              ORRS     r1,r1,r2
;;;1521   
;;;1522     /* Write to TIMx CCMR1 register */
;;;1523     TIMx->CCMR1 = tmpccmr1;
000010  8301              STRH     r1,[r0,#0x18]
;;;1524   }
000012  4770              BX       lr
;;;1525   
                          ENDP


                          AREA ||i.TIM_ClearOC3Ref||, CODE, READONLY, ALIGN=1

                  TIM_ClearOC3Ref PROC
;;;1534     */
;;;1535   void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
000000  8b82              LDRH     r2,[r0,#0x1c]
;;;1536   {
;;;1537     uint16_t tmpccmr2 = 0;
;;;1538   
;;;1539     /* Check the parameters */
;;;1540     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1541     assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
;;;1542   
;;;1543     tmpccmr2 = TIMx->CCMR2;
;;;1544   
;;;1545     /* Reset the OC3CE Bit */
;;;1546     tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE;
000002  f0220280          BIC      r2,r2,#0x80
;;;1547   
;;;1548     /* Enable or Disable the Output Compare Clear Bit */
;;;1549     tmpccmr2 |= TIM_OCClear;
000006  430a              ORRS     r2,r2,r1
;;;1550   
;;;1551     /* Write to TIMx CCMR2 register */
;;;1552     TIMx->CCMR2 = tmpccmr2;
000008  8382              STRH     r2,[r0,#0x1c]
;;;1553   }
00000a  4770              BX       lr
;;;1554   
                          ENDP


                          AREA ||i.TIM_ClearOC4Ref||, CODE, READONLY, ALIGN=1

                  TIM_ClearOC4Ref PROC
;;;1563     */
;;;1564   void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
000000  8b82              LDRH     r2,[r0,#0x1c]
;;;1565   {
;;;1566     uint16_t tmpccmr2 = 0;
;;;1567   
;;;1568     /* Check the parameters */
;;;1569     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1570     assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
;;;1571   
;;;1572     tmpccmr2 = TIMx->CCMR2;
;;;1573   
;;;1574     /* Reset the OC4CE Bit */
;;;1575     tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE;
000002  f3c2020e          UBFX     r2,r2,#0,#15
;;;1576   
;;;1577     /* Enable or Disable the Output Compare Clear Bit */
;;;1578     tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
000006  f64f73ff          MOV      r3,#0xffff
00000a  ea032101          AND      r1,r3,r1,LSL #8
00000e  4311              ORRS     r1,r1,r2
;;;1579   
;;;1580     /* Write to TIMx CCMR2 register */
;;;1581     TIMx->CCMR2 = tmpccmr2;
000010  8381              STRH     r1,[r0,#0x1c]
;;;1582   }
000012  4770              BX       lr
;;;1583   
                          ENDP


                          AREA ||i.TIM_Cmd||, CODE, READONLY, ALIGN=1

                  TIM_Cmd PROC
;;;591      */
;;;592    void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;593    {
000002  d004              BEQ      |L17.14|
;;;594      /* Check the parameters */
;;;595      assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
;;;596      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;597      
;;;598      if (NewState != DISABLE)
;;;599      {
;;;600        /* Enable the TIM Counter */
;;;601        TIMx->CR1 |= TIM_CR1_CEN;
000004  8801              LDRH     r1,[r0,#0]
000006  f0410101          ORR      r1,r1,#1
00000a  8001              STRH     r1,[r0,#0]
;;;602      }
;;;603      else
;;;604      {
;;;605        /* Disable the TIM Counter */
;;;606        TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN;
;;;607      }
;;;608    }
00000c  4770              BX       lr
                  |L17.14|
00000e  8801              LDRH     r1,[r0,#0]            ;606
000010  f0210101          BIC      r1,r1,#1              ;606
000014  8001              STRH     r1,[r0,#0]            ;606
000016  4770              BX       lr
;;;609    /**
                          ENDP


                          AREA ||i.TIM_CounterModeConfig||, CODE, READONLY, ALIGN=1

                  TIM_CounterModeConfig PROC
;;;382      */
;;;383    void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
000000  8802              LDRH     r2,[r0,#0]
;;;384    {
;;;385      uint16_t tmpcr1 = 0;
;;;386    
;;;387      /* Check the parameters */
;;;388      assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;389      assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
;;;390    
;;;391      tmpcr1 = TIMx->CR1;
;;;392    
;;;393      /* Reset the CMS and DIR Bits */
;;;394      tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS);
000002  f0220270          BIC      r2,r2,#0x70
;;;395    
;;;396      /* Set the Counter Mode */
;;;397      tmpcr1 |= TIM_CounterMode;
000006  430a              ORRS     r2,r2,r1
;;;398    
;;;399      /* Write to TIMx CR1 register */
;;;400      TIMx->CR1 = tmpcr1;
000008  8002              STRH     r2,[r0,#0]
;;;401    }
00000a  4770              BX       lr
;;;402    
                          ENDP


                          AREA ||i.TIM_CtrlPWMOutputs||, CODE, READONLY, ALIGN=1

                  TIM_CtrlPWMOutputs PROC
;;;2264     */
;;;2265   void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;2266   {
000002  d005              BEQ      |L19.16|
;;;2267     /* Check the parameters */
;;;2268     assert_param(IS_TIM_LIST4_PERIPH(TIMx));
;;;2269     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2270   
;;;2271     if (NewState != DISABLE)
;;;2272     {
;;;2273       /* Enable the TIM Main Output */
;;;2274       TIMx->BDTR |= TIM_BDTR_MOE;
000004  f8301f44          LDRH     r1,[r0,#0x44]!
000008  f4414100          ORR      r1,r1,#0x8000
00000c  8001              STRH     r1,[r0,#0]
;;;2275     }
;;;2276     else
;;;2277     {
;;;2278       /* Disable the TIM Main Output */
;;;2279       TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE;
;;;2280     }  
;;;2281   }
00000e  4770              BX       lr
                  |L19.16|
000010  f8301f44          LDRH     r1,[r0,#0x44]!        ;2279
000014  f3c1010e          UBFX     r1,r1,#0,#15          ;2279
000018  8001              STRH     r1,[r0,#0]            ;2279
00001a  4770              BX       lr
;;;2282   
                          ENDP


                          AREA ||i.TIM_DMACmd||, CODE, READONLY, ALIGN=1

                  TIM_DMACmd PROC
;;;2617     */
;;;2618   void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
000000  2a00              CMP      r2,#0
;;;2619   { 
000002  d003              BEQ      |L20.12|
;;;2620     /* Check the parameters */
;;;2621     assert_param(IS_TIM_LIST5_PERIPH(TIMx)); 
;;;2622     assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
;;;2623     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2624     
;;;2625     if (NewState != DISABLE)
;;;2626     {
;;;2627       /* Enable the DMA sources */
;;;2628       TIMx->DIER |= TIM_DMASource; 
000004  8982              LDRH     r2,[r0,#0xc]
000006  430a              ORRS     r2,r2,r1
000008  8182              STRH     r2,[r0,#0xc]
;;;2629     }
;;;2630     else
;;;2631     {
;;;2632       /* Disable the DMA sources */
;;;2633       TIMx->DIER &= (uint16_t)~TIM_DMASource;
;;;2634     }
;;;2635   }
00000a  4770              BX       lr
                  |L20.12|
00000c  8982              LDRH     r2,[r0,#0xc]          ;2633
00000e  438a              BICS     r2,r2,r1              ;2633
000010  8182              STRH     r2,[r0,#0xc]          ;2633
000012  4770              BX       lr
;;;2636   
                          ENDP


                          AREA ||i.TIM_DMAConfig||, CODE, READONLY, ALIGN=1

                  TIM_DMAConfig PROC
;;;2590     */
;;;2591   void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
000000  4311              ORRS     r1,r1,r2
;;;2592   {
;;;2593     /* Check the parameters */
;;;2594     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2595     assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); 
;;;2596     assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
;;;2597   
;;;2598     /* Set the DMA Base and the DMA Burst Length */
;;;2599     TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
000002  f8a01048          STRH     r1,[r0,#0x48]
;;;2600   }
000006  4770              BX       lr
;;;2601   
                          ENDP


                          AREA ||i.TIM_DeInit||, CODE, READONLY, ALIGN=2

                  TIM_DeInit PROC
;;;199      */
;;;200    void TIM_DeInit(TIM_TypeDef* TIMx)
000000  b510              PUSH     {r4,lr}
;;;201    {
;;;202      /* Check the parameters */
;;;203      assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
;;;204     
;;;205      if (TIMx == TIM1)
000002  495d              LDR      r1,|L22.376|
000004  4288              CMP      r0,r1
000006  d109              BNE      |L22.28|
;;;206      {
;;;207        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
000008  2101              MOVS     r1,#1
00000a  4608              MOV      r0,r1
00000c  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;208        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);  
000010  2100              MOVS     r1,#0
000012  e8bd4010          POP      {r4,lr}
000016  2001              MOVS     r0,#1
000018  f7ffbffe          B.W      RCC_APB2PeriphResetCmd
                  |L22.28|
;;;209      } 
;;;210      else if (TIMx == TIM2) 
00001c  f1b04f80          CMP      r0,#0x40000000
000020  d00c              BEQ      |L22.60|
;;;211      {     
;;;212        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
;;;213        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
;;;214      }  
;;;215      else if (TIMx == TIM3)
000022  4956              LDR      r1,|L22.380|
000024  4288              CMP      r0,r1
000026  d113              BNE      |L22.80|
;;;216      { 
;;;217        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
000028  2101              MOVS     r1,#1
00002a  2002              MOVS     r0,#2
00002c  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;218        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
000030  2100              MOVS     r1,#0
000032  e8bd4010          POP      {r4,lr}
000036  2002              MOVS     r0,#2
000038  f7ffbffe          B.W      RCC_APB1PeriphResetCmd
                  |L22.60|
00003c  2101              MOVS     r1,#1                 ;212
00003e  4608              MOV      r0,r1                 ;212
000040  f7fffffe          BL       RCC_APB1PeriphResetCmd
000044  2100              MOVS     r1,#0                 ;213
000046  e8bd4010          POP      {r4,lr}               ;213
00004a  2001              MOVS     r0,#1                 ;213
00004c  f7ffbffe          B.W      RCC_APB1PeriphResetCmd
                  |L22.80|
;;;219      }  
;;;220      else if (TIMx == TIM4)
000050  494b              LDR      r1,|L22.384|
000052  4288              CMP      r0,r1
000054  d109              BNE      |L22.106|
;;;221      { 
;;;222        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
000056  2101              MOVS     r1,#1
000058  2004              MOVS     r0,#4
00005a  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;223        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
00005e  2100              MOVS     r1,#0
000060  e8bd4010          POP      {r4,lr}
000064  2004              MOVS     r0,#4
000066  f7ffbffe          B.W      RCC_APB1PeriphResetCmd
                  |L22.106|
;;;224      }  
;;;225      else if (TIMx == TIM5)
00006a  4946              LDR      r1,|L22.388|
00006c  4288              CMP      r0,r1
00006e  d109              BNE      |L22.132|
;;;226      {      
;;;227        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
000070  2101              MOVS     r1,#1
000072  2008              MOVS     r0,#8
000074  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;228        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
000078  2100              MOVS     r1,#0
00007a  e8bd4010          POP      {r4,lr}
00007e  2008              MOVS     r0,#8
000080  f7ffbffe          B.W      RCC_APB1PeriphResetCmd
                  |L22.132|
;;;229      }  
;;;230      else if (TIMx == TIM6)  
000084  4940              LDR      r1,|L22.392|
000086  4288              CMP      r0,r1
000088  d109              BNE      |L22.158|
;;;231      {    
;;;232        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
00008a  2101              MOVS     r1,#1
00008c  2010              MOVS     r0,#0x10
00008e  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;233        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
000092  2100              MOVS     r1,#0
000094  e8bd4010          POP      {r4,lr}
000098  2010              MOVS     r0,#0x10
00009a  f7ffbffe          B.W      RCC_APB1PeriphResetCmd
                  |L22.158|
;;;234      }  
;;;235      else if (TIMx == TIM7)
00009e  493b              LDR      r1,|L22.396|
0000a0  4288              CMP      r0,r1
0000a2  d109              BNE      |L22.184|
;;;236      {      
;;;237        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
0000a4  2101              MOVS     r1,#1
0000a6  2020              MOVS     r0,#0x20
0000a8  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;238        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
0000ac  2100              MOVS     r1,#0
0000ae  e8bd4010          POP      {r4,lr}
0000b2  2020              MOVS     r0,#0x20
0000b4  f7ffbffe          B.W      RCC_APB1PeriphResetCmd
                  |L22.184|
;;;239      }  
;;;240      else if (TIMx == TIM8)
0000b8  4935              LDR      r1,|L22.400|
0000ba  4288              CMP      r0,r1
0000bc  d109              BNE      |L22.210|
;;;241      {      
;;;242        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
0000be  2101              MOVS     r1,#1
0000c0  2002              MOVS     r0,#2
0000c2  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;243        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);  
0000c6  2100              MOVS     r1,#0
0000c8  e8bd4010          POP      {r4,lr}
0000cc  2002              MOVS     r0,#2
0000ce  f7ffbffe          B.W      RCC_APB2PeriphResetCmd
                  |L22.210|
;;;244      }  
;;;245      else if (TIMx == TIM9)
0000d2  4930              LDR      r1,|L22.404|
0000d4  4288              CMP      r0,r1
0000d6  d10a              BNE      |L22.238|
;;;246      {      
;;;247        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
0000d8  2101              MOVS     r1,#1
0000da  040c              LSLS     r4,r1,#16
0000dc  4620              MOV      r0,r4
0000de  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;248        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);  
0000e2  4620              MOV      r0,r4
0000e4  e8bd4010          POP      {r4,lr}
0000e8  2100              MOVS     r1,#0
0000ea  f7ffbffe          B.W      RCC_APB2PeriphResetCmd
                  |L22.238|
;;;249       }  
;;;250      else if (TIMx == TIM10)
0000ee  492a              LDR      r1,|L22.408|
0000f0  4288              CMP      r0,r1
0000f2  d10a              BNE      |L22.266|
;;;251      {      
;;;252        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
0000f4  2101              MOVS     r1,#1
0000f6  044c              LSLS     r4,r1,#17
0000f8  4620              MOV      r0,r4
0000fa  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;253        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);  
0000fe  4620              MOV      r0,r4
000100  e8bd4010          POP      {r4,lr}
000104  2100              MOVS     r1,#0
000106  f7ffbffe          B.W      RCC_APB2PeriphResetCmd
                  |L22.266|
;;;254      }  
;;;255      else if (TIMx == TIM11) 
00010a  4924              LDR      r1,|L22.412|
00010c  4288              CMP      r0,r1
00010e  d10a              BNE      |L22.294|
;;;256      {     
;;;257        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
000110  2101              MOVS     r1,#1
000112  048c              LSLS     r4,r1,#18
000114  4620              MOV      r0,r4
000116  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;258        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);  
00011a  4620              MOV      r0,r4
00011c  e8bd4010          POP      {r4,lr}
000120  2100              MOVS     r1,#0
000122  f7ffbffe          B.W      RCC_APB2PeriphResetCmd
                  |L22.294|
;;;259      }  
;;;260      else if (TIMx == TIM12)
000126  491e              LDR      r1,|L22.416|
000128  4288              CMP      r0,r1
00012a  d109              BNE      |L22.320|
;;;261      {      
;;;262        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
00012c  2101              MOVS     r1,#1
00012e  2040              MOVS     r0,#0x40
000130  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;263        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);  
000134  2100              MOVS     r1,#0
000136  e8bd4010          POP      {r4,lr}
00013a  2040              MOVS     r0,#0x40
00013c  f7ffbffe          B.W      RCC_APB1PeriphResetCmd
                  |L22.320|
;;;264      }  
;;;265      else if (TIMx == TIM13) 
000140  4918              LDR      r1,|L22.420|
000142  4288              CMP      r0,r1
000144  d109              BNE      |L22.346|
;;;266      {       
;;;267        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
000146  2101              MOVS     r1,#1
000148  2080              MOVS     r0,#0x80
00014a  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;268        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);  
00014e  2100              MOVS     r1,#0
000150  e8bd4010          POP      {r4,lr}
000154  2080              MOVS     r0,#0x80
000156  f7ffbffe          B.W      RCC_APB1PeriphResetCmd
                  |L22.346|
;;;269      }  
;;;270      else
;;;271      { 
;;;272        if (TIMx == TIM14) 
00015a  4913              LDR      r1,|L22.424|
00015c  4288              CMP      r0,r1
00015e  d10a              BNE      |L22.374|
;;;273        {     
;;;274          RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
000160  1584              ASRS     r4,r0,#22
000162  2101              MOVS     r1,#1
000164  4620              MOV      r0,r4
000166  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;275          RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); 
00016a  4620              MOV      r0,r4
00016c  e8bd4010          POP      {r4,lr}
000170  2100              MOVS     r1,#0
000172  f7ffbffe          B.W      RCC_APB1PeriphResetCmd
                  |L22.374|
;;;276        }   
;;;277      }
;;;278    }
000176  bd10              POP      {r4,pc}
;;;279    
                          ENDP

                  |L22.376|
                          DCD      0x40010000
                  |L22.380|
                          DCD      0x40000400
                  |L22.384|
                          DCD      0x40000800
                  |L22.388|
                          DCD      0x40000c00
                  |L22.392|
                          DCD      0x40001000
                  |L22.396|
                          DCD      0x40001400
                  |L22.400|
                          DCD      0x40010400
                  |L22.404|
                          DCD      0x40014000
                  |L22.408|
                          DCD      0x40014400
                  |L22.412|
                          DCD      0x40014800
                  |L22.416|
                          DCD      0x40001800
                  |L22.420|
                          DCD      0x40001c00
                  |L22.424|
                          DCD      0x40002000

                          AREA ||i.TIM_ETRClockMode1Config||, CODE, READONLY, ALIGN=1

                  TIM_ETRClockMode1Config PROC
;;;2773     */
;;;2774   void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
000000  b510              PUSH     {r4,lr}
;;;2775                               uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
;;;2776   {
000002  4604              MOV      r4,r0
;;;2777     uint16_t tmpsmcr = 0;
;;;2778   
;;;2779     /* Check the parameters */
;;;2780     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2781     assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;2782     assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;2783     assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;2784     /* Configure the ETR Clock source */
;;;2785     TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
000004  4620              MOV      r0,r4
000006  f7fffffe          BL       TIM_ETRConfig
;;;2786     
;;;2787     /* Get the TIMx SMCR register value */
;;;2788     tmpsmcr = TIMx->SMCR;
00000a  8920              LDRH     r0,[r4,#8]
;;;2789   
;;;2790     /* Reset the SMS Bits */
;;;2791     tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
00000c  f0200007          BIC      r0,r0,#7
;;;2792   
;;;2793     /* Select the External clock mode1 */
;;;2794     tmpsmcr |= TIM_SlaveMode_External1;
000010  f0400007          ORR      r0,r0,#7
;;;2795   
;;;2796     /* Select the Trigger selection : ETRF */
;;;2797     tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
000014  f0200070          BIC      r0,r0,#0x70
;;;2798     tmpsmcr |= TIM_TS_ETRF;
000018  f0400070          ORR      r0,r0,#0x70
;;;2799   
;;;2800     /* Write to TIMx SMCR */
;;;2801     TIMx->SMCR = tmpsmcr;
00001c  8120              STRH     r0,[r4,#8]
;;;2802   }
00001e  bd10              POP      {r4,pc}
;;;2803   
                          ENDP


                          AREA ||i.TIM_ETRClockMode2Config||, CODE, READONLY, ALIGN=1

                  TIM_ETRClockMode2Config PROC
;;;2820     */
;;;2821   void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
000000  b510              PUSH     {r4,lr}
;;;2822                                uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
;;;2823   {
000002  4604              MOV      r4,r0
;;;2824     /* Check the parameters */
;;;2825     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2826     assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;2827     assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;2828     assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;2829   
;;;2830     /* Configure the ETR Clock source */
;;;2831     TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
000004  4620              MOV      r0,r4
000006  f7fffffe          BL       TIM_ETRConfig
;;;2832   
;;;2833     /* Enable the External clock mode2 */
;;;2834     TIMx->SMCR |= TIM_SMCR_ECE;
00000a  8920              LDRH     r0,[r4,#8]
00000c  f4404080          ORR      r0,r0,#0x4000
000010  8120              STRH     r0,[r4,#8]
;;;2835   }
000012  bd10              POP      {r4,pc}
;;;2836   /**
                          ENDP


                          AREA ||i.TIM_ETRConfig||, CODE, READONLY, ALIGN=1

                  TIM_ETRConfig PROC
;;;3011     */
;;;3012   void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
000000  b530              PUSH     {r4,r5,lr}
;;;3013                      uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
;;;3014   {
;;;3015     uint16_t tmpsmcr = 0;
;;;3016   
;;;3017     /* Check the parameters */
;;;3018     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;3019     assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;3020     assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;3021     assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;3022   
;;;3023     tmpsmcr = TIMx->SMCR;
000002  8904              LDRH     r4,[r0,#8]
;;;3024   
;;;3025     /* Reset the ETR Bits */
;;;3026     tmpsmcr &= SMCR_ETR_MASK;
000004  b2e4              UXTB     r4,r4
;;;3027   
;;;3028     /* Set the Prescaler, the Filter value and the Polarity */
;;;3029     tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
000006  f64f75ff          MOV      r5,#0xffff
00000a  ea052303          AND      r3,r5,r3,LSL #8
00000e  4313              ORRS     r3,r3,r2
000010  430b              ORRS     r3,r3,r1
000012  4323              ORRS     r3,r3,r4
;;;3030   
;;;3031     /* Write to TIMx SMCR */
;;;3032     TIMx->SMCR = tmpsmcr;
000014  8103              STRH     r3,[r0,#8]
;;;3033   }
000016  bd30              POP      {r4,r5,pc}
;;;3034   /**
                          ENDP


                          AREA ||i.TIM_EncoderInterfaceConfig||, CODE, READONLY, ALIGN=1

                  TIM_EncoderInterfaceConfig PROC
;;;3069     */
;;;3070   void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
000000  b570              PUSH     {r4-r6,lr}
;;;3071                                   uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
;;;3072   {
;;;3073     uint16_t tmpsmcr = 0;
;;;3074     uint16_t tmpccmr1 = 0;
;;;3075     uint16_t tmpccer = 0;
;;;3076       
;;;3077     /* Check the parameters */
;;;3078     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;3079     assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
;;;3080     assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
;;;3081     assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
;;;3082   
;;;3083     /* Get the TIMx SMCR register value */
;;;3084     tmpsmcr = TIMx->SMCR;
000002  8905              LDRH     r5,[r0,#8]
;;;3085   
;;;3086     /* Get the TIMx CCMR1 register value */
;;;3087     tmpccmr1 = TIMx->CCMR1;
000004  8b04              LDRH     r4,[r0,#0x18]
;;;3088   
;;;3089     /* Get the TIMx CCER register value */
;;;3090     tmpccer = TIMx->CCER;
000006  8c06              LDRH     r6,[r0,#0x20]
;;;3091   
;;;3092     /* Set the encoder Mode */
;;;3093     tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
000008  f0250507          BIC      r5,r5,#7
;;;3094     tmpsmcr |= TIM_EncoderMode;
00000c  430d              ORRS     r5,r5,r1
;;;3095   
;;;3096     /* Select the Capture Compare 1 and the Capture Compare 2 as input */
;;;3097     tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S);
00000e  f64f41fc          MOV      r1,#0xfcfc
000012  400c              ANDS     r4,r4,r1
;;;3098     tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
000014  f2401101          MOV      r1,#0x101
000018  430c              ORRS     r4,r4,r1
;;;3099   
;;;3100     /* Set the TI1 and the TI2 Polarities */
;;;3101     tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P);
00001a  f0260622          BIC      r6,r6,#0x22
;;;3102     tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
00001e  f64f71ff          MOV      r1,#0xffff
000022  ea011103          AND      r1,r1,r3,LSL #4
000026  4311              ORRS     r1,r1,r2
000028  4331              ORRS     r1,r1,r6
;;;3103   
;;;3104     /* Write to TIMx SMCR */
;;;3105     TIMx->SMCR = tmpsmcr;
00002a  8105              STRH     r5,[r0,#8]
;;;3106   
;;;3107     /* Write to TIMx CCMR1 */
;;;3108     TIMx->CCMR1 = tmpccmr1;
00002c  8304              STRH     r4,[r0,#0x18]
;;;3109   
;;;3110     /* Write to TIMx CCER */
;;;3111     TIMx->CCER = tmpccer;
00002e  8401              STRH     r1,[r0,#0x20]
;;;3112   }
000030  bd70              POP      {r4-r6,pc}
;;;3113   
                          ENDP


                          AREA ||i.TIM_ForcedOC1Config||, CODE, READONLY, ALIGN=1

                  TIM_ForcedOC1Config PROC
;;;1123     */
;;;1124   void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
000000  8b02              LDRH     r2,[r0,#0x18]
;;;1125   {
;;;1126     uint16_t tmpccmr1 = 0;
;;;1127   
;;;1128     /* Check the parameters */
;;;1129     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;1130     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1131     tmpccmr1 = TIMx->CCMR1;
;;;1132   
;;;1133     /* Reset the OC1M Bits */
;;;1134     tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M;
000002  f0220270          BIC      r2,r2,#0x70
;;;1135   
;;;1136     /* Configure The Forced output Mode */
;;;1137     tmpccmr1 |= TIM_ForcedAction;
000006  430a              ORRS     r2,r2,r1
;;;1138   
;;;1139     /* Write to TIMx CCMR1 register */
;;;1140     TIMx->CCMR1 = tmpccmr1;
000008  8302              STRH     r2,[r0,#0x18]
;;;1141   }
00000a  4770              BX       lr
;;;1142   
                          ENDP


                          AREA ||i.TIM_ForcedOC2Config||, CODE, READONLY, ALIGN=1

                  TIM_ForcedOC2Config PROC
;;;1152     */
;;;1153   void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
000000  8b02              LDRH     r2,[r0,#0x18]
;;;1154   {
;;;1155     uint16_t tmpccmr1 = 0;
;;;1156   
;;;1157     /* Check the parameters */
;;;1158     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;1159     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1160     tmpccmr1 = TIMx->CCMR1;
;;;1161   
;;;1162     /* Reset the OC2M Bits */
;;;1163     tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M;
000002  f42242e0          BIC      r2,r2,#0x7000
;;;1164   
;;;1165     /* Configure The Forced output Mode */
;;;1166     tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
000006  f64f73ff          MOV      r3,#0xffff
00000a  ea032101          AND      r1,r3,r1,LSL #8
00000e  4311              ORRS     r1,r1,r2
;;;1167   
;;;1168     /* Write to TIMx CCMR1 register */
;;;1169     TIMx->CCMR1 = tmpccmr1;
000010  8301              STRH     r1,[r0,#0x18]
;;;1170   }
000012  4770              BX       lr
;;;1171   
                          ENDP


                          AREA ||i.TIM_ForcedOC3Config||, CODE, READONLY, ALIGN=1

                  TIM_ForcedOC3Config PROC
;;;1180     */
;;;1181   void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
000000  8b82              LDRH     r2,[r0,#0x1c]
;;;1182   {
;;;1183     uint16_t tmpccmr2 = 0;
;;;1184   
;;;1185     /* Check the parameters */
;;;1186     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1187     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1188   
;;;1189     tmpccmr2 = TIMx->CCMR2;
;;;1190   
;;;1191     /* Reset the OC1M Bits */
;;;1192     tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M;
000002  f0220270          BIC      r2,r2,#0x70
;;;1193   
;;;1194     /* Configure The Forced output Mode */
;;;1195     tmpccmr2 |= TIM_ForcedAction;
000006  430a              ORRS     r2,r2,r1
;;;1196   
;;;1197     /* Write to TIMx CCMR2 register */
;;;1198     TIMx->CCMR2 = tmpccmr2;
000008  8382              STRH     r2,[r0,#0x1c]
;;;1199   }
00000a  4770              BX       lr
;;;1200   
                          ENDP


                          AREA ||i.TIM_ForcedOC4Config||, CODE, READONLY, ALIGN=1

                  TIM_ForcedOC4Config PROC
;;;1209     */
;;;1210   void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
000000  8b82              LDRH     r2,[r0,#0x1c]
;;;1211   {
;;;1212     uint16_t tmpccmr2 = 0;
;;;1213   
;;;1214     /* Check the parameters */
;;;1215     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1216     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1217     tmpccmr2 = TIMx->CCMR2;
;;;1218   
;;;1219     /* Reset the OC2M Bits */
;;;1220     tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M;
000002  f42242e0          BIC      r2,r2,#0x7000
;;;1221   
;;;1222     /* Configure The Forced output Mode */
;;;1223     tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
000006  f64f73ff          MOV      r3,#0xffff
00000a  ea032101          AND      r1,r3,r1,LSL #8
00000e  4311              ORRS     r1,r1,r2
;;;1224   
;;;1225     /* Write to TIMx CCMR2 register */
;;;1226     TIMx->CCMR2 = tmpccmr2;
000010  8381              STRH     r1,[r0,#0x1c]
;;;1227   }
000012  4770              BX       lr
;;;1228   
                          ENDP


                          AREA ||i.TIM_GenerateEvent||, CODE, READONLY, ALIGN=1

                  TIM_GenerateEvent PROC
;;;2409     */
;;;2410   void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
000000  8281              STRH     r1,[r0,#0x14]
;;;2411   { 
;;;2412     /* Check the parameters */
;;;2413     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2414     assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
;;;2415    
;;;2416     /* Set the event sources */
;;;2417     TIMx->EGR = TIM_EventSource;
;;;2418   }
000002  4770              BX       lr
;;;2419   
                          ENDP


                          AREA ||i.TIM_GetCapture1||, CODE, READONLY, ALIGN=1

                  TIM_GetCapture1 PROC
;;;2031     */
;;;2032   uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
000000  6b40              LDR      r0,[r0,#0x34]
;;;2033   {
;;;2034     /* Check the parameters */
;;;2035     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;2036   
;;;2037     /* Get the Capture 1 Register value */
;;;2038     return TIMx->CCR1;
;;;2039   }
000002  4770              BX       lr
;;;2040   
                          ENDP


                          AREA ||i.TIM_GetCapture2||, CODE, READONLY, ALIGN=1

                  TIM_GetCapture2 PROC
;;;2046     */
;;;2047   uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
000000  6b80              LDR      r0,[r0,#0x38]
;;;2048   {
;;;2049     /* Check the parameters */
;;;2050     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;2051   
;;;2052     /* Get the Capture 2 Register value */
;;;2053     return TIMx->CCR2;
;;;2054   }
000002  4770              BX       lr
;;;2055   
                          ENDP


                          AREA ||i.TIM_GetCapture3||, CODE, READONLY, ALIGN=1

                  TIM_GetCapture3 PROC
;;;2060     */
;;;2061   uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
000000  6bc0              LDR      r0,[r0,#0x3c]
;;;2062   {
;;;2063     /* Check the parameters */
;;;2064     assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
;;;2065   
;;;2066     /* Get the Capture 3 Register value */
;;;2067     return TIMx->CCR3;
;;;2068   }
000002  4770              BX       lr
;;;2069   
                          ENDP


                          AREA ||i.TIM_GetCapture4||, CODE, READONLY, ALIGN=1

                  TIM_GetCapture4 PROC
;;;2074     */
;;;2075   uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
000000  6c00              LDR      r0,[r0,#0x40]
;;;2076   {
;;;2077     /* Check the parameters */
;;;2078     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2079   
;;;2080     /* Get the Capture 4 Register value */
;;;2081     return TIMx->CCR4;
;;;2082   }
000002  4770              BX       lr
;;;2083   
                          ENDP


                          AREA ||i.TIM_GetCounter||, CODE, READONLY, ALIGN=1

                  TIM_GetCounter PROC
;;;437      */
;;;438    uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
000000  6a40              LDR      r0,[r0,#0x24]
;;;439    {
;;;440      /* Check the parameters */
;;;441      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;442    
;;;443      /* Get the Counter Register value */
;;;444      return TIMx->CNT;
;;;445    }
000002  4770              BX       lr
;;;446    
                          ENDP


                          AREA ||i.TIM_GetFlagStatus||, CODE, READONLY, ALIGN=1

                  TIM_GetFlagStatus PROC
;;;2442     */
;;;2443   FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
000000  4602              MOV      r2,r0
;;;2444   { 
;;;2445     ITStatus bitstatus = RESET;  
000002  2000              MOVS     r0,#0
;;;2446     /* Check the parameters */
;;;2447     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2448     assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
;;;2449   
;;;2450     
;;;2451     if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
000004  8a12              LDRH     r2,[r2,#0x10]
000006  420a              TST      r2,r1
000008  d000              BEQ      |L37.12|
;;;2452     {
;;;2453       bitstatus = SET;
00000a  2001              MOVS     r0,#1
                  |L37.12|
;;;2454     }
;;;2455     else
;;;2456     {
;;;2457       bitstatus = RESET;
;;;2458     }
;;;2459     return bitstatus;
;;;2460   }
00000c  4770              BX       lr
;;;2461   
                          ENDP


                          AREA ||i.TIM_GetITStatus||, CODE, READONLY, ALIGN=1

                  TIM_GetITStatus PROC
;;;2512     */
;;;2513   ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
000000  4602              MOV      r2,r0
;;;2514   {
;;;2515     ITStatus bitstatus = RESET;  
000002  2000              MOVS     r0,#0
;;;2516     uint16_t itstatus = 0x0, itenable = 0x0;
;;;2517     /* Check the parameters */
;;;2518     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2519     assert_param(IS_TIM_GET_IT(TIM_IT));
;;;2520      
;;;2521     itstatus = TIMx->SR & TIM_IT;
000004  8a13              LDRH     r3,[r2,#0x10]
000006  400b              ANDS     r3,r3,r1
;;;2522     
;;;2523     itenable = TIMx->DIER & TIM_IT;
000008  8992              LDRH     r2,[r2,#0xc]
00000a  400a              ANDS     r2,r2,r1
;;;2524     if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
00000c  2b00              CMP      r3,#0
00000e  d002              BEQ      |L38.22|
000010  2a00              CMP      r2,#0
000012  d000              BEQ      |L38.22|
;;;2525     {
;;;2526       bitstatus = SET;
000014  2001              MOVS     r0,#1
                  |L38.22|
;;;2527     }
;;;2528     else
;;;2529     {
;;;2530       bitstatus = RESET;
;;;2531     }
;;;2532     return bitstatus;
;;;2533   }
000016  4770              BX       lr
;;;2534   
                          ENDP


                          AREA ||i.TIM_GetPrescaler||, CODE, READONLY, ALIGN=1

                  TIM_GetPrescaler PROC
;;;451      */
;;;452    uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
000000  8d00              LDRH     r0,[r0,#0x28]
;;;453    {
;;;454      /* Check the parameters */
;;;455      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;456    
;;;457      /* Get the Prescaler Register value */
;;;458      return TIMx->PSC;
;;;459    }
000002  4770              BX       lr
;;;460    
                          ENDP


                          AREA ||i.TIM_ICInit||, CODE, READONLY, ALIGN=1

                  TIM_ICInit PROC
;;;1899     */
;;;1900   void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
000000  b570              PUSH     {r4-r6,lr}
;;;1901   {
000002  4606              MOV      r6,r0
000004  460c              MOV      r4,r1
;;;1902     /* Check the parameters */
;;;1903     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;1904     assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
;;;1905     assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
;;;1906     assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
;;;1907     assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
;;;1908     
;;;1909     if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
000006  8825              LDRH     r5,[r4,#0]
;;;1910     {
;;;1911       /* TI1 Configuration */
;;;1912       TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
000008  8861              LDRH     r1,[r4,#2]
00000a  88a2              LDRH     r2,[r4,#4]
00000c  8923              LDRH     r3,[r4,#8]
00000e  2d00              CMP      r5,#0                 ;1909
000010  d00c              BEQ      |L40.44|
;;;1913                  TIM_ICInitStruct->TIM_ICSelection,
;;;1914                  TIM_ICInitStruct->TIM_ICFilter);
;;;1915       /* Set the Input Capture Prescaler value */
;;;1916       TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
;;;1917     }
;;;1918     else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
000012  2d04              CMP      r5,#4
000014  d013              BEQ      |L40.62|
;;;1919     {
;;;1920       /* TI2 Configuration */
;;;1921       assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;1922       TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
;;;1923                  TIM_ICInitStruct->TIM_ICSelection,
;;;1924                  TIM_ICInitStruct->TIM_ICFilter);
;;;1925       /* Set the Input Capture Prescaler value */
;;;1926       TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
;;;1927     }
;;;1928     else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
000016  2d08              CMP      r5,#8
000018  d01a              BEQ      |L40.80|
;;;1929     {
;;;1930       /* TI3 Configuration */
;;;1931       assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1932       TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,
;;;1933                  TIM_ICInitStruct->TIM_ICSelection,
;;;1934                  TIM_ICInitStruct->TIM_ICFilter);
;;;1935       /* Set the Input Capture Prescaler value */
;;;1936       TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
;;;1937     }
;;;1938     else
;;;1939     {
;;;1940       /* TI4 Configuration */
;;;1941       assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1942       TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
00001a  4630              MOV      r0,r6
00001c  f7fffffe          BL       TI4_Config
;;;1943                  TIM_ICInitStruct->TIM_ICSelection,
;;;1944                  TIM_ICInitStruct->TIM_ICFilter);
;;;1945       /* Set the Input Capture Prescaler value */
;;;1946       TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000020  88e1              LDRH     r1,[r4,#6]
000022  4630              MOV      r0,r6
000024  e8bd4070          POP      {r4-r6,lr}
000028  f7ffbffe          B.W      TIM_SetIC4Prescaler
                  |L40.44|
00002c  4630              MOV      r0,r6                 ;1912
00002e  f7fffffe          BL       TI1_Config
000032  88e1              LDRH     r1,[r4,#6]            ;1916
000034  4630              MOV      r0,r6                 ;1916
000036  e8bd4070          POP      {r4-r6,lr}            ;1916
00003a  f7ffbffe          B.W      TIM_SetIC1Prescaler
                  |L40.62|
00003e  4630              MOV      r0,r6                 ;1922
000040  f7fffffe          BL       TI2_Config
000044  88e1              LDRH     r1,[r4,#6]            ;1926
000046  4630              MOV      r0,r6                 ;1926
000048  e8bd4070          POP      {r4-r6,lr}            ;1926
00004c  f7ffbffe          B.W      TIM_SetIC2Prescaler
                  |L40.80|
000050  4630              MOV      r0,r6                 ;1932
000052  f7fffffe          BL       TI3_Config
000056  88e1              LDRH     r1,[r4,#6]            ;1936
000058  4630              MOV      r0,r6                 ;1936
00005a  e8bd4070          POP      {r4-r6,lr}            ;1936
00005e  f7ffbffe          B.W      TIM_SetIC3Prescaler
;;;1947     }
;;;1948   }
;;;1949   
                          ENDP


                          AREA ||i.TIM_ICStructInit||, CODE, READONLY, ALIGN=1

                  TIM_ICStructInit PROC
;;;1955     */
;;;1956   void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
000000  2100              MOVS     r1,#0
;;;1957   {
;;;1958     /* Set the default configuration */
;;;1959     TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
000002  8001              STRH     r1,[r0,#0]
;;;1960     TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
000004  8041              STRH     r1,[r0,#2]
;;;1961     TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
000006  2201              MOVS     r2,#1
000008  8082              STRH     r2,[r0,#4]
;;;1962     TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
00000a  80c1              STRH     r1,[r0,#6]
;;;1963     TIM_ICInitStruct->TIM_ICFilter = 0x00;
00000c  8101              STRH     r1,[r0,#8]
;;;1964   }
00000e  4770              BX       lr
;;;1965   
                          ENDP


                          AREA ||i.TIM_ITConfig||, CODE, READONLY, ALIGN=1

                  TIM_ITConfig PROC
;;;2371     */
;;;2372   void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
000000  2a00              CMP      r2,#0
;;;2373   {  
000002  d003              BEQ      |L42.12|
;;;2374     /* Check the parameters */
;;;2375     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2376     assert_param(IS_TIM_IT(TIM_IT));
;;;2377     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2378     
;;;2379     if (NewState != DISABLE)
;;;2380     {
;;;2381       /* Enable the Interrupt sources */
;;;2382       TIMx->DIER |= TIM_IT;
000004  8982              LDRH     r2,[r0,#0xc]
000006  430a              ORRS     r2,r2,r1
000008  8182              STRH     r2,[r0,#0xc]
;;;2383     }
;;;2384     else
;;;2385     {
;;;2386       /* Disable the Interrupt sources */
;;;2387       TIMx->DIER &= (uint16_t)~TIM_IT;
;;;2388     }
;;;2389   }
00000a  4770              BX       lr
                  |L42.12|
00000c  8982              LDRH     r2,[r0,#0xc]          ;2387
00000e  438a              BICS     r2,r2,r1              ;2387
000010  8182              STRH     r2,[r0,#0xc]          ;2387
000012  4770              BX       lr
;;;2390   
                          ENDP


                          AREA ||i.TIM_ITRxExternalClockConfig||, CODE, READONLY, ALIGN=1

                  TIM_ITRxExternalClockConfig PROC
;;;2703     */
;;;2704   void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
000000  b500              PUSH     {lr}
;;;2705   {
000002  4603              MOV      r3,r0
;;;2706     /* Check the parameters */
;;;2707     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;2708     assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
;;;2709   
;;;2710     /* Select the Internal Trigger */
;;;2711     TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
000004  4618              MOV      r0,r3
000006  f7fffffe          BL       TIM_SelectInputTrigger
;;;2712   
;;;2713     /* Select the External clock mode1 */
;;;2714     TIMx->SMCR |= TIM_SlaveMode_External1;
00000a  8918              LDRH     r0,[r3,#8]
00000c  f0400007          ORR      r0,r0,#7
000010  8118              STRH     r0,[r3,#8]
;;;2715   }
000012  bd00              POP      {pc}
;;;2716   
                          ENDP


                          AREA ||i.TIM_InternalClockConfig||, CODE, READONLY, ALIGN=1

                  TIM_InternalClockConfig PROC
;;;2682     */
;;;2683   void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
000000  8901              LDRH     r1,[r0,#8]
;;;2684   {
;;;2685     /* Check the parameters */
;;;2686     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;2687   
;;;2688     /* Disable slave mode to clock the prescaler directly with the internal clock */
;;;2689     TIMx->SMCR &=  (uint16_t)~TIM_SMCR_SMS;
000002  f0210107          BIC      r1,r1,#7
000006  8101              STRH     r1,[r0,#8]
;;;2690   }
000008  4770              BX       lr
;;;2691   
                          ENDP


                          AREA ||i.TIM_OC1FastConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC1FastConfig PROC
;;;1354     */
;;;1355   void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
000000  8b02              LDRH     r2,[r0,#0x18]
;;;1356   {
;;;1357     uint16_t tmpccmr1 = 0;
;;;1358   
;;;1359     /* Check the parameters */
;;;1360     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;1361     assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
;;;1362   
;;;1363     /* Get the TIMx CCMR1 register value */
;;;1364     tmpccmr1 = TIMx->CCMR1;
;;;1365   
;;;1366     /* Reset the OC1FE Bit */
;;;1367     tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE;
000002  f0220204          BIC      r2,r2,#4
;;;1368   
;;;1369     /* Enable or Disable the Output Compare Fast Bit */
;;;1370     tmpccmr1 |= TIM_OCFast;
000006  430a              ORRS     r2,r2,r1
;;;1371   
;;;1372     /* Write to TIMx CCMR1 */
;;;1373     TIMx->CCMR1 = tmpccmr1;
000008  8302              STRH     r2,[r0,#0x18]
;;;1374   }
00000a  4770              BX       lr
;;;1375   
                          ENDP


                          AREA ||i.TIM_OC1Init||, CODE, READONLY, ALIGN=2

                  TIM_OC1Init PROC
;;;672      */
;;;673    void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
000000  b530              PUSH     {r4,r5,lr}
;;;674    {
;;;675      uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
;;;676       
;;;677      /* Check the parameters */
;;;678      assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 
;;;679      assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;680      assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;681      assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
;;;682    
;;;683      /* Disable the Channel 1: Reset the CC1E Bit */
;;;684      TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
000002  8c02              LDRH     r2,[r0,#0x20]
000004  f0220201          BIC      r2,r2,#1
000008  8402              STRH     r2,[r0,#0x20]
;;;685      
;;;686      /* Get the TIMx CCER register value */
;;;687      tmpccer = TIMx->CCER;
00000a  8c05              LDRH     r5,[r0,#0x20]
;;;688      /* Get the TIMx CR2 register value */
;;;689      tmpcr2 =  TIMx->CR2;
00000c  8883              LDRH     r3,[r0,#4]
;;;690      
;;;691      /* Get the TIMx CCMR1 register value */
;;;692      tmpccmrx = TIMx->CCMR1;
00000e  8b02              LDRH     r2,[r0,#0x18]
;;;693        
;;;694      /* Reset the Output Compare Mode Bits */
;;;695      tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M;
000010  f0220270          BIC      r2,r2,#0x70
;;;696      tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S;
000014  f0220203          BIC      r2,r2,#3
;;;697      /* Select the Output Compare Mode */
;;;698      tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
000018  880c              LDRH     r4,[r1,#0]
00001a  4314              ORRS     r4,r4,r2
;;;699      
;;;700      /* Reset the Output Polarity level */
;;;701      tmpccer &= (uint16_t)~TIM_CCER_CC1P;
00001c  f0250202          BIC      r2,r5,#2
;;;702      /* Set the Output Compare Polarity */
;;;703      tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
000020  898d              LDRH     r5,[r1,#0xc]
000022  4315              ORRS     r5,r5,r2
;;;704      
;;;705      /* Set the Output State */
;;;706      tmpccer |= TIM_OCInitStruct->TIM_OutputState;
000024  884a              LDRH     r2,[r1,#2]
000026  432a              ORRS     r2,r2,r5
;;;707        
;;;708      if((TIMx == TIM1) || (TIMx == TIM8))
000028  4d0d              LDR      r5,|L46.96|
00002a  42a8              CMP      r0,r5
00002c  d002              BEQ      |L46.52|
00002e  4d0d              LDR      r5,|L46.100|
000030  42a8              CMP      r0,r5
000032  d10f              BNE      |L46.84|
                  |L46.52|
;;;709      {
;;;710        assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
;;;711        assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
;;;712        assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
;;;713        assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;714        
;;;715        /* Reset the Output N Polarity level */
;;;716        tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
000034  f0220508          BIC      r5,r2,#8
;;;717        /* Set the Output N Polarity */
;;;718        tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
000038  89ca              LDRH     r2,[r1,#0xe]
00003a  432a              ORRS     r2,r2,r5
;;;719        /* Reset the Output N State */
;;;720        tmpccer &= (uint16_t)~TIM_CCER_CC1NE;
00003c  f0220504          BIC      r5,r2,#4
;;;721        
;;;722        /* Set the Output N State */
;;;723        tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
000040  888a              LDRH     r2,[r1,#4]
000042  432a              ORRS     r2,r2,r5
;;;724        /* Reset the Output Compare and Output Compare N IDLE State */
;;;725        tmpcr2 &= (uint16_t)~TIM_CR2_OIS1;
000044  f4237380          BIC      r3,r3,#0x100
;;;726        tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N;
000048  f4237300          BIC      r3,r3,#0x200
;;;727        /* Set the Output Idle state */
;;;728        tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
00004c  8a0d              LDRH     r5,[r1,#0x10]
00004e  431d              ORRS     r5,r5,r3
;;;729        /* Set the Output N Idle state */
;;;730        tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
000050  8a4b              LDRH     r3,[r1,#0x12]
000052  432b              ORRS     r3,r3,r5
                  |L46.84|
;;;731      }
;;;732      /* Write to TIMx CR2 */
;;;733      TIMx->CR2 = tmpcr2;
000054  8083              STRH     r3,[r0,#4]
;;;734      
;;;735      /* Write to TIMx CCMR1 */
;;;736      TIMx->CCMR1 = tmpccmrx;
000056  8304              STRH     r4,[r0,#0x18]
;;;737      
;;;738      /* Set the Capture Compare Register value */
;;;739      TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
000058  6889              LDR      r1,[r1,#8]
00005a  6341              STR      r1,[r0,#0x34]
;;;740      
;;;741      /* Write to TIMx CCER */
;;;742      TIMx->CCER = tmpccer;
00005c  8402              STRH     r2,[r0,#0x20]
;;;743    }
00005e  bd30              POP      {r4,r5,pc}
;;;744    
                          ENDP

                  |L46.96|
                          DCD      0x40010000
                  |L46.100|
                          DCD      0x40010400

                          AREA ||i.TIM_OC1NPolarityConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC1NPolarityConfig PROC
;;;1619     */
;;;1620   void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
000000  8c02              LDRH     r2,[r0,#0x20]
;;;1621   {
;;;1622     uint16_t tmpccer = 0;
;;;1623     /* Check the parameters */
;;;1624     assert_param(IS_TIM_LIST4_PERIPH(TIMx));
;;;1625     assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
;;;1626      
;;;1627     tmpccer = TIMx->CCER;
;;;1628   
;;;1629     /* Set or Reset the CC1NP Bit */
;;;1630     tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
000002  f0220208          BIC      r2,r2,#8
;;;1631     tmpccer |= TIM_OCNPolarity;
000006  430a              ORRS     r2,r2,r1
;;;1632   
;;;1633     /* Write to TIMx CCER register */
;;;1634     TIMx->CCER = tmpccer;
000008  8402              STRH     r2,[r0,#0x20]
;;;1635   }
00000a  4770              BX       lr
;;;1636   
                          ENDP


                          AREA ||i.TIM_OC1PolarityConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC1PolarityConfig PROC
;;;1592     */
;;;1593   void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
000000  8c02              LDRH     r2,[r0,#0x20]
;;;1594   {
;;;1595     uint16_t tmpccer = 0;
;;;1596   
;;;1597     /* Check the parameters */
;;;1598     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;1599     assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
;;;1600   
;;;1601     tmpccer = TIMx->CCER;
;;;1602   
;;;1603     /* Set or Reset the CC1P Bit */
;;;1604     tmpccer &= (uint16_t)(~TIM_CCER_CC1P);
000002  f0220202          BIC      r2,r2,#2
;;;1605     tmpccer |= TIM_OCPolarity;
000006  430a              ORRS     r2,r2,r1
;;;1606   
;;;1607     /* Write to TIMx CCER register */
;;;1608     TIMx->CCER = tmpccer;
000008  8402              STRH     r2,[r0,#0x20]
;;;1609   }
00000a  4770              BX       lr
;;;1610   
                          ENDP


                          AREA ||i.TIM_OC1PreloadConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC1PreloadConfig PROC
;;;1237     */
;;;1238   void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
000000  8b02              LDRH     r2,[r0,#0x18]
;;;1239   {
;;;1240     uint16_t tmpccmr1 = 0;
;;;1241   
;;;1242     /* Check the parameters */
;;;1243     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;1244     assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
;;;1245   
;;;1246     tmpccmr1 = TIMx->CCMR1;
;;;1247   
;;;1248     /* Reset the OC1PE Bit */
;;;1249     tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE);
000002  f0220208          BIC      r2,r2,#8
;;;1250   
;;;1251     /* Enable or Disable the Output Compare Preload feature */
;;;1252     tmpccmr1 |= TIM_OCPreload;
000006  430a              ORRS     r2,r2,r1
;;;1253   
;;;1254     /* Write to TIMx CCMR1 register */
;;;1255     TIMx->CCMR1 = tmpccmr1;
000008  8302              STRH     r2,[r0,#0x18]
;;;1256   }
00000a  4770              BX       lr
;;;1257   
                          ENDP


                          AREA ||i.TIM_OC2FastConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC2FastConfig PROC
;;;1385     */
;;;1386   void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
000000  8b02              LDRH     r2,[r0,#0x18]
;;;1387   {
;;;1388     uint16_t tmpccmr1 = 0;
;;;1389   
;;;1390     /* Check the parameters */
;;;1391     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;1392     assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
;;;1393   
;;;1394     /* Get the TIMx CCMR1 register value */
;;;1395     tmpccmr1 = TIMx->CCMR1;
;;;1396   
;;;1397     /* Reset the OC2FE Bit */
;;;1398     tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE);
000002  f4226280          BIC      r2,r2,#0x400
;;;1399   
;;;1400     /* Enable or Disable the Output Compare Fast Bit */
;;;1401     tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
000006  f64f73ff          MOV      r3,#0xffff
00000a  ea032101          AND      r1,r3,r1,LSL #8
00000e  4311              ORRS     r1,r1,r2
;;;1402   
;;;1403     /* Write to TIMx CCMR1 */
;;;1404     TIMx->CCMR1 = tmpccmr1;
000010  8301              STRH     r1,[r0,#0x18]
;;;1405   }
000012  4770              BX       lr
;;;1406   
                          ENDP


                          AREA ||i.TIM_OC2Init||, CODE, READONLY, ALIGN=2

                  TIM_OC2Init PROC
;;;753      */
;;;754    void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
000000  b570              PUSH     {r4-r6,lr}
;;;755    {
;;;756      uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
;;;757       
;;;758      /* Check the parameters */
;;;759      assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 
;;;760      assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;761      assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;762      assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
;;;763    
;;;764      /* Disable the Channel 2: Reset the CC2E Bit */
;;;765      TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
000002  8c02              LDRH     r2,[r0,#0x20]
000004  f0220210          BIC      r2,r2,#0x10
000008  8402              STRH     r2,[r0,#0x20]
;;;766      
;;;767      /* Get the TIMx CCER register value */  
;;;768      tmpccer = TIMx->CCER;
00000a  8c02              LDRH     r2,[r0,#0x20]
;;;769      /* Get the TIMx CR2 register value */
;;;770      tmpcr2 =  TIMx->CR2;
00000c  8883              LDRH     r3,[r0,#4]
;;;771      
;;;772      /* Get the TIMx CCMR1 register value */
;;;773      tmpccmrx = TIMx->CCMR1;
00000e  8b04              LDRH     r4,[r0,#0x18]
;;;774        
;;;775      /* Reset the Output Compare mode and Capture/Compare selection Bits */
;;;776      tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M;
000010  f42444e0          BIC      r4,r4,#0x7000
;;;777      tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S;
000014  f4247640          BIC      r6,r4,#0x300
;;;778      
;;;779      /* Select the Output Compare Mode */
;;;780      tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
000018  880d              LDRH     r5,[r1,#0]
00001a  f64f74ff          MOV      r4,#0xffff
00001e  ea042505          AND      r5,r4,r5,LSL #8
000022  4335              ORRS     r5,r5,r6
;;;781      
;;;782      /* Reset the Output Polarity level */
;;;783      tmpccer &= (uint16_t)~TIM_CCER_CC2P;
000024  f0220220          BIC      r2,r2,#0x20
;;;784      /* Set the Output Compare Polarity */
;;;785      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
000028  898e              LDRH     r6,[r1,#0xc]
00002a  ea041606          AND      r6,r4,r6,LSL #4
00002e  4316              ORRS     r6,r6,r2
;;;786      
;;;787      /* Set the Output State */
;;;788      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
000030  884a              LDRH     r2,[r1,#2]
000032  ea041202          AND      r2,r4,r2,LSL #4
000036  4332              ORRS     r2,r2,r6
;;;789        
;;;790      if((TIMx == TIM1) || (TIMx == TIM8))
000038  4e11              LDR      r6,|L51.128|
00003a  42b0              CMP      r0,r6
00003c  d002              BEQ      |L51.68|
00003e  4e11              LDR      r6,|L51.132|
000040  42b0              CMP      r0,r6
000042  d117              BNE      |L51.116|
                  |L51.68|
;;;791      {
;;;792        assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
;;;793        assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
;;;794        assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
;;;795        assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;796        
;;;797        /* Reset the Output N Polarity level */
;;;798        tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
000044  f0220280          BIC      r2,r2,#0x80
;;;799        /* Set the Output N Polarity */
;;;800        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
000048  89ce              LDRH     r6,[r1,#0xe]
00004a  ea041606          AND      r6,r4,r6,LSL #4
00004e  4316              ORRS     r6,r6,r2
;;;801        /* Reset the Output N State */
;;;802        tmpccer &= (uint16_t)~TIM_CCER_CC2NE;
000050  f0260640          BIC      r6,r6,#0x40
;;;803        
;;;804        /* Set the Output N State */
;;;805        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
000054  888a              LDRH     r2,[r1,#4]
000056  ea041202          AND      r2,r4,r2,LSL #4
00005a  4332              ORRS     r2,r2,r6
;;;806        /* Reset the Output Compare and Output Compare N IDLE State */
;;;807        tmpcr2 &= (uint16_t)~TIM_CR2_OIS2;
00005c  f4236380          BIC      r3,r3,#0x400
;;;808        tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N;
000060  f4236300          BIC      r3,r3,#0x800
;;;809        /* Set the Output Idle state */
;;;810        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
000064  8a0e              LDRH     r6,[r1,#0x10]
000066  ea040686          AND      r6,r4,r6,LSL #2
00006a  431e              ORRS     r6,r6,r3
;;;811        /* Set the Output N Idle state */
;;;812        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
00006c  8a4b              LDRH     r3,[r1,#0x12]
00006e  ea040383          AND      r3,r4,r3,LSL #2
000072  4333              ORRS     r3,r3,r6
                  |L51.116|
;;;813      }
;;;814      /* Write to TIMx CR2 */
;;;815      TIMx->CR2 = tmpcr2;
000074  8083              STRH     r3,[r0,#4]
;;;816      
;;;817      /* Write to TIMx CCMR1 */
;;;818      TIMx->CCMR1 = tmpccmrx;
000076  8305              STRH     r5,[r0,#0x18]
;;;819      
;;;820      /* Set the Capture Compare Register value */
;;;821      TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
000078  6889              LDR      r1,[r1,#8]
00007a  6381              STR      r1,[r0,#0x38]
;;;822      
;;;823      /* Write to TIMx CCER */
;;;824      TIMx->CCER = tmpccer;
00007c  8402              STRH     r2,[r0,#0x20]
;;;825    }
00007e  bd70              POP      {r4-r6,pc}
;;;826    
                          ENDP

                  |L51.128|
                          DCD      0x40010000
                  |L51.132|
                          DCD      0x40010400

                          AREA ||i.TIM_OC2NPolarityConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC2NPolarityConfig PROC
;;;1673     */
;;;1674   void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
000000  8c02              LDRH     r2,[r0,#0x20]
;;;1675   {
;;;1676     uint16_t tmpccer = 0;
;;;1677   
;;;1678     /* Check the parameters */
;;;1679     assert_param(IS_TIM_LIST4_PERIPH(TIMx));
;;;1680     assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
;;;1681     
;;;1682     tmpccer = TIMx->CCER;
;;;1683   
;;;1684     /* Set or Reset the CC2NP Bit */
;;;1685     tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
000002  f0220280          BIC      r2,r2,#0x80
;;;1686     tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
000006  f64f73ff          MOV      r3,#0xffff
00000a  ea031101          AND      r1,r3,r1,LSL #4
00000e  4311              ORRS     r1,r1,r2
;;;1687   
;;;1688     /* Write to TIMx CCER register */
;;;1689     TIMx->CCER = tmpccer;
000010  8401              STRH     r1,[r0,#0x20]
;;;1690   }
000012  4770              BX       lr
;;;1691   
                          ENDP


                          AREA ||i.TIM_OC2PolarityConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC2PolarityConfig PROC
;;;1646     */
;;;1647   void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
000000  8c02              LDRH     r2,[r0,#0x20]
;;;1648   {
;;;1649     uint16_t tmpccer = 0;
;;;1650   
;;;1651     /* Check the parameters */
;;;1652     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;1653     assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
;;;1654   
;;;1655     tmpccer = TIMx->CCER;
;;;1656   
;;;1657     /* Set or Reset the CC2P Bit */
;;;1658     tmpccer &= (uint16_t)(~TIM_CCER_CC2P);
000002  f0220220          BIC      r2,r2,#0x20
;;;1659     tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
000006  f64f73ff          MOV      r3,#0xffff
00000a  ea031101          AND      r1,r3,r1,LSL #4
00000e  4311              ORRS     r1,r1,r2
;;;1660   
;;;1661     /* Write to TIMx CCER register */
;;;1662     TIMx->CCER = tmpccer;
000010  8401              STRH     r1,[r0,#0x20]
;;;1663   }
000012  4770              BX       lr
;;;1664   
                          ENDP


                          AREA ||i.TIM_OC2PreloadConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC2PreloadConfig PROC
;;;1267     */
;;;1268   void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
000000  8b02              LDRH     r2,[r0,#0x18]
;;;1269   {
;;;1270     uint16_t tmpccmr1 = 0;
;;;1271   
;;;1272     /* Check the parameters */
;;;1273     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;1274     assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
;;;1275   
;;;1276     tmpccmr1 = TIMx->CCMR1;
;;;1277   
;;;1278     /* Reset the OC2PE Bit */
;;;1279     tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE);
000002  f4226200          BIC      r2,r2,#0x800
;;;1280   
;;;1281     /* Enable or Disable the Output Compare Preload feature */
;;;1282     tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
000006  f64f73ff          MOV      r3,#0xffff
00000a  ea032101          AND      r1,r3,r1,LSL #8
00000e  4311              ORRS     r1,r1,r2
;;;1283   
;;;1284     /* Write to TIMx CCMR1 register */
;;;1285     TIMx->CCMR1 = tmpccmr1;
000010  8301              STRH     r1,[r0,#0x18]
;;;1286   }
000012  4770              BX       lr
;;;1287   
                          ENDP


                          AREA ||i.TIM_OC3FastConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC3FastConfig PROC
;;;1415     */
;;;1416   void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
000000  8b82              LDRH     r2,[r0,#0x1c]
;;;1417   {
;;;1418     uint16_t tmpccmr2 = 0;
;;;1419     
;;;1420     /* Check the parameters */
;;;1421     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1422     assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
;;;1423   
;;;1424     /* Get the TIMx CCMR2 register value */
;;;1425     tmpccmr2 = TIMx->CCMR2;
;;;1426   
;;;1427     /* Reset the OC3FE Bit */
;;;1428     tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE;
000002  f0220204          BIC      r2,r2,#4
;;;1429   
;;;1430     /* Enable or Disable the Output Compare Fast Bit */
;;;1431     tmpccmr2 |= TIM_OCFast;
000006  430a              ORRS     r2,r2,r1
;;;1432   
;;;1433     /* Write to TIMx CCMR2 */
;;;1434     TIMx->CCMR2 = tmpccmr2;
000008  8382              STRH     r2,[r0,#0x1c]
;;;1435   }
00000a  4770              BX       lr
;;;1436   
                          ENDP


                          AREA ||i.TIM_OC3Init||, CODE, READONLY, ALIGN=2

                  TIM_OC3Init PROC
;;;834      */
;;;835    void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
000000  b570              PUSH     {r4-r6,lr}
;;;836    {
;;;837      uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
;;;838       
;;;839      /* Check the parameters */
;;;840      assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
;;;841      assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;842      assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;843      assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
;;;844    
;;;845      /* Disable the Channel 3: Reset the CC2E Bit */
;;;846      TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
000002  8c02              LDRH     r2,[r0,#0x20]
000004  f4227280          BIC      r2,r2,#0x100
000008  8402              STRH     r2,[r0,#0x20]
;;;847      
;;;848      /* Get the TIMx CCER register value */
;;;849      tmpccer = TIMx->CCER;
00000a  8c02              LDRH     r2,[r0,#0x20]
;;;850      /* Get the TIMx CR2 register value */
;;;851      tmpcr2 =  TIMx->CR2;
00000c  8883              LDRH     r3,[r0,#4]
;;;852      
;;;853      /* Get the TIMx CCMR2 register value */
;;;854      tmpccmrx = TIMx->CCMR2;
00000e  8b84              LDRH     r4,[r0,#0x1c]
;;;855        
;;;856      /* Reset the Output Compare mode and Capture/Compare selection Bits */
;;;857      tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M;
000010  f0240470          BIC      r4,r4,#0x70
;;;858      tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S;  
000014  f0240403          BIC      r4,r4,#3
;;;859      /* Select the Output Compare Mode */
;;;860      tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
000018  880d              LDRH     r5,[r1,#0]
00001a  4325              ORRS     r5,r5,r4
;;;861      
;;;862      /* Reset the Output Polarity level */
;;;863      tmpccer &= (uint16_t)~TIM_CCER_CC3P;
00001c  f4227200          BIC      r2,r2,#0x200
;;;864      /* Set the Output Compare Polarity */
;;;865      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
000020  898e              LDRH     r6,[r1,#0xc]
000022  f64f74ff          MOV      r4,#0xffff
000026  ea042606          AND      r6,r4,r6,LSL #8
00002a  4316              ORRS     r6,r6,r2
;;;866      
;;;867      /* Set the Output State */
;;;868      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
00002c  884a              LDRH     r2,[r1,#2]
00002e  ea042202          AND      r2,r4,r2,LSL #8
000032  4332              ORRS     r2,r2,r6
;;;869        
;;;870      if((TIMx == TIM1) || (TIMx == TIM8))
000034  4e11              LDR      r6,|L56.124|
000036  42b0              CMP      r0,r6
000038  d002              BEQ      |L56.64|
00003a  4e11              LDR      r6,|L56.128|
00003c  42b0              CMP      r0,r6
00003e  d117              BNE      |L56.112|
                  |L56.64|
;;;871      {
;;;872        assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
;;;873        assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
;;;874        assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
;;;875        assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;876        
;;;877        /* Reset the Output N Polarity level */
;;;878        tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
000040  f4226600          BIC      r6,r2,#0x800
;;;879        /* Set the Output N Polarity */
;;;880        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
000044  89ca              LDRH     r2,[r1,#0xe]
000046  ea042202          AND      r2,r4,r2,LSL #8
00004a  4332              ORRS     r2,r2,r6
;;;881        /* Reset the Output N State */
;;;882        tmpccer &= (uint16_t)~TIM_CCER_CC3NE;
00004c  f4226680          BIC      r6,r2,#0x400
;;;883        
;;;884        /* Set the Output N State */
;;;885        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
000050  888a              LDRH     r2,[r1,#4]
000052  ea042202          AND      r2,r4,r2,LSL #8
000056  4332              ORRS     r2,r2,r6
;;;886        /* Reset the Output Compare and Output Compare N IDLE State */
;;;887        tmpcr2 &= (uint16_t)~TIM_CR2_OIS3;
000058  f4235380          BIC      r3,r3,#0x1000
;;;888        tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N;
00005c  f4235300          BIC      r3,r3,#0x2000
;;;889        /* Set the Output Idle state */
;;;890        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
000060  8a0e              LDRH     r6,[r1,#0x10]
000062  ea041606          AND      r6,r4,r6,LSL #4
000066  431e              ORRS     r6,r6,r3
;;;891        /* Set the Output N Idle state */
;;;892        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
000068  8a4b              LDRH     r3,[r1,#0x12]
00006a  ea041303          AND      r3,r4,r3,LSL #4
00006e  4333              ORRS     r3,r3,r6
                  |L56.112|
;;;893      }
;;;894      /* Write to TIMx CR2 */
;;;895      TIMx->CR2 = tmpcr2;
000070  8083              STRH     r3,[r0,#4]
;;;896      
;;;897      /* Write to TIMx CCMR2 */
;;;898      TIMx->CCMR2 = tmpccmrx;
000072  8385              STRH     r5,[r0,#0x1c]
;;;899      
;;;900      /* Set the Capture Compare Register value */
;;;901      TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
000074  6889              LDR      r1,[r1,#8]
000076  63c1              STR      r1,[r0,#0x3c]
;;;902      
;;;903      /* Write to TIMx CCER */
;;;904      TIMx->CCER = tmpccer;
000078  8402              STRH     r2,[r0,#0x20]
;;;905    }
00007a  bd70              POP      {r4-r6,pc}
;;;906    
                          ENDP

                  |L56.124|
                          DCD      0x40010000
                  |L56.128|
                          DCD      0x40010400

                          AREA ||i.TIM_OC3NPolarityConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC3NPolarityConfig PROC
;;;1727     */
;;;1728   void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
000000  8c02              LDRH     r2,[r0,#0x20]
;;;1729   {
;;;1730     uint16_t tmpccer = 0;
;;;1731    
;;;1732     /* Check the parameters */
;;;1733     assert_param(IS_TIM_LIST4_PERIPH(TIMx));
;;;1734     assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
;;;1735       
;;;1736     tmpccer = TIMx->CCER;
;;;1737   
;;;1738     /* Set or Reset the CC3NP Bit */
;;;1739     tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
000002  f4226200          BIC      r2,r2,#0x800
;;;1740     tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
000006  f64f73ff          MOV      r3,#0xffff
00000a  ea032101          AND      r1,r3,r1,LSL #8
00000e  4311              ORRS     r1,r1,r2
;;;1741   
;;;1742     /* Write to TIMx CCER register */
;;;1743     TIMx->CCER = tmpccer;
000010  8401              STRH     r1,[r0,#0x20]
;;;1744   }
000012  4770              BX       lr
;;;1745   
                          ENDP


                          AREA ||i.TIM_OC3PolarityConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC3PolarityConfig PROC
;;;1700     */
;;;1701   void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
000000  8c02              LDRH     r2,[r0,#0x20]
;;;1702   {
;;;1703     uint16_t tmpccer = 0;
;;;1704   
;;;1705     /* Check the parameters */
;;;1706     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1707     assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
;;;1708   
;;;1709     tmpccer = TIMx->CCER;
;;;1710   
;;;1711     /* Set or Reset the CC3P Bit */
;;;1712     tmpccer &= (uint16_t)~TIM_CCER_CC3P;
000002  f4227200          BIC      r2,r2,#0x200
;;;1713     tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
000006  f64f73ff          MOV      r3,#0xffff
00000a  ea032101          AND      r1,r3,r1,LSL #8
00000e  4311              ORRS     r1,r1,r2
;;;1714   
;;;1715     /* Write to TIMx CCER register */
;;;1716     TIMx->CCER = tmpccer;
000010  8401              STRH     r1,[r0,#0x20]
;;;1717   }
000012  4770              BX       lr
;;;1718   
                          ENDP


                          AREA ||i.TIM_OC3PreloadConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC3PreloadConfig PROC
;;;1296     */
;;;1297   void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
000000  8b82              LDRH     r2,[r0,#0x1c]
;;;1298   {
;;;1299     uint16_t tmpccmr2 = 0;
;;;1300   
;;;1301     /* Check the parameters */
;;;1302     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1303     assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
;;;1304   
;;;1305     tmpccmr2 = TIMx->CCMR2;
;;;1306   
;;;1307     /* Reset the OC3PE Bit */
;;;1308     tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE);
000002  f0220208          BIC      r2,r2,#8
;;;1309   
;;;1310     /* Enable or Disable the Output Compare Preload feature */
;;;1311     tmpccmr2 |= TIM_OCPreload;
000006  430a              ORRS     r2,r2,r1
;;;1312   
;;;1313     /* Write to TIMx CCMR2 register */
;;;1314     TIMx->CCMR2 = tmpccmr2;
000008  8382              STRH     r2,[r0,#0x1c]
;;;1315   }
00000a  4770              BX       lr
;;;1316   
                          ENDP


                          AREA ||i.TIM_OC4FastConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC4FastConfig PROC
;;;1445     */
;;;1446   void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
000000  8b82              LDRH     r2,[r0,#0x1c]
;;;1447   {
;;;1448     uint16_t tmpccmr2 = 0;
;;;1449   
;;;1450     /* Check the parameters */
;;;1451     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1452     assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
;;;1453   
;;;1454     /* Get the TIMx CCMR2 register value */
;;;1455     tmpccmr2 = TIMx->CCMR2;
;;;1456   
;;;1457     /* Reset the OC4FE Bit */
;;;1458     tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE);
000002  f4226280          BIC      r2,r2,#0x400
;;;1459   
;;;1460     /* Enable or Disable the Output Compare Fast Bit */
;;;1461     tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
000006  f64f73ff          MOV      r3,#0xffff
00000a  ea032101          AND      r1,r3,r1,LSL #8
00000e  4311              ORRS     r1,r1,r2
;;;1462   
;;;1463     /* Write to TIMx CCMR2 */
;;;1464     TIMx->CCMR2 = tmpccmr2;
000010  8381              STRH     r1,[r0,#0x1c]
;;;1465   }
000012  4770              BX       lr
;;;1466   
                          ENDP


                          AREA ||i.TIM_OC4Init||, CODE, READONLY, ALIGN=2

                  TIM_OC4Init PROC
;;;914      */
;;;915    void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
000000  b570              PUSH     {r4-r6,lr}
;;;916    {
;;;917      uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
;;;918       
;;;919      /* Check the parameters */
;;;920      assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
;;;921      assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;922      assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;923      assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
;;;924    
;;;925      /* Disable the Channel 4: Reset the CC4E Bit */
;;;926      TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
000002  8c02              LDRH     r2,[r0,#0x20]
000004  f4225280          BIC      r2,r2,#0x1000
000008  8402              STRH     r2,[r0,#0x20]
;;;927      
;;;928      /* Get the TIMx CCER register value */
;;;929      tmpccer = TIMx->CCER;
00000a  8c05              LDRH     r5,[r0,#0x20]
;;;930      /* Get the TIMx CR2 register value */
;;;931      tmpcr2 =  TIMx->CR2;
00000c  8882              LDRH     r2,[r0,#4]
;;;932      
;;;933      /* Get the TIMx CCMR2 register value */
;;;934      tmpccmrx = TIMx->CCMR2;
00000e  8b83              LDRH     r3,[r0,#0x1c]
;;;935        
;;;936      /* Reset the Output Compare mode and Capture/Compare selection Bits */
;;;937      tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M;
000010  f42343e0          BIC      r3,r3,#0x7000
;;;938      tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S;
000014  f4237640          BIC      r6,r3,#0x300
;;;939      
;;;940      /* Select the Output Compare Mode */
;;;941      tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
000018  880c              LDRH     r4,[r1,#0]
00001a  f64f73ff          MOV      r3,#0xffff
00001e  ea032404          AND      r4,r3,r4,LSL #8
000022  4334              ORRS     r4,r4,r6
;;;942      
;;;943      /* Reset the Output Polarity level */
;;;944      tmpccer &= (uint16_t)~TIM_CCER_CC4P;
000024  f4255500          BIC      r5,r5,#0x2000
;;;945      /* Set the Output Compare Polarity */
;;;946      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
000028  898e              LDRH     r6,[r1,#0xc]
00002a  ea033606          AND      r6,r3,r6,LSL #12
00002e  432e              ORRS     r6,r6,r5
;;;947      
;;;948      /* Set the Output State */
;;;949      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
000030  884d              LDRH     r5,[r1,#2]
000032  ea033505          AND      r5,r3,r5,LSL #12
000036  4335              ORRS     r5,r5,r6
;;;950      
;;;951      if((TIMx == TIM1) || (TIMx == TIM8))
000038  4e08              LDR      r6,|L61.92|
00003a  42b0              CMP      r0,r6
00003c  d002              BEQ      |L61.68|
00003e  4e08              LDR      r6,|L61.96|
000040  42b0              CMP      r0,r6
000042  d105              BNE      |L61.80|
                  |L61.68|
;;;952      {
;;;953        assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;954        /* Reset the Output Compare IDLE State */
;;;955        tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4;
000044  f4224680          BIC      r6,r2,#0x4000
;;;956        /* Set the Output Idle state */
;;;957        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
000048  8a0a              LDRH     r2,[r1,#0x10]
00004a  ea031282          AND      r2,r3,r2,LSL #6
00004e  4332              ORRS     r2,r2,r6
                  |L61.80|
;;;958      }
;;;959      /* Write to TIMx CR2 */
;;;960      TIMx->CR2 = tmpcr2;
000050  8082              STRH     r2,[r0,#4]
;;;961      
;;;962      /* Write to TIMx CCMR2 */  
;;;963      TIMx->CCMR2 = tmpccmrx;
000052  8384              STRH     r4,[r0,#0x1c]
;;;964        
;;;965      /* Set the Capture Compare Register value */
;;;966      TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
000054  6889              LDR      r1,[r1,#8]
000056  6401              STR      r1,[r0,#0x40]
;;;967      
;;;968      /* Write to TIMx CCER */
;;;969      TIMx->CCER = tmpccer;
000058  8405              STRH     r5,[r0,#0x20]
;;;970    }
00005a  bd70              POP      {r4-r6,pc}
;;;971    
                          ENDP

                  |L61.92|
                          DCD      0x40010000
                  |L61.96|
                          DCD      0x40010400

                          AREA ||i.TIM_OC4PolarityConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC4PolarityConfig PROC
;;;1754     */
;;;1755   void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
000000  8c02              LDRH     r2,[r0,#0x20]
;;;1756   {
;;;1757     uint16_t tmpccer = 0;
;;;1758   
;;;1759     /* Check the parameters */
;;;1760     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1761     assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
;;;1762   
;;;1763     tmpccer = TIMx->CCER;
;;;1764   
;;;1765     /* Set or Reset the CC4P Bit */
;;;1766     tmpccer &= (uint16_t)~TIM_CCER_CC4P;
000002  f4225200          BIC      r2,r2,#0x2000
;;;1767     tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
000006  f64f73ff          MOV      r3,#0xffff
00000a  ea033101          AND      r1,r3,r1,LSL #12
00000e  4311              ORRS     r1,r1,r2
;;;1768   
;;;1769     /* Write to TIMx CCER register */
;;;1770     TIMx->CCER = tmpccer;
000010  8401              STRH     r1,[r0,#0x20]
;;;1771   }
000012  4770              BX       lr
;;;1772   
                          ENDP


                          AREA ||i.TIM_OC4PreloadConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC4PreloadConfig PROC
;;;1325     */
;;;1326   void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
000000  8b82              LDRH     r2,[r0,#0x1c]
;;;1327   {
;;;1328     uint16_t tmpccmr2 = 0;
;;;1329   
;;;1330     /* Check the parameters */
;;;1331     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1332     assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
;;;1333   
;;;1334     tmpccmr2 = TIMx->CCMR2;
;;;1335   
;;;1336     /* Reset the OC4PE Bit */
;;;1337     tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE);
000002  f4226200          BIC      r2,r2,#0x800
;;;1338   
;;;1339     /* Enable or Disable the Output Compare Preload feature */
;;;1340     tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
000006  f64f73ff          MOV      r3,#0xffff
00000a  ea032101          AND      r1,r3,r1,LSL #8
00000e  4311              ORRS     r1,r1,r2
;;;1341   
;;;1342     /* Write to TIMx CCMR2 register */
;;;1343     TIMx->CCMR2 = tmpccmr2;
000010  8381              STRH     r1,[r0,#0x1c]
;;;1344   }
000012  4770              BX       lr
;;;1345   
                          ENDP


                          AREA ||i.TIM_OCStructInit||, CODE, READONLY, ALIGN=1

                  TIM_OCStructInit PROC
;;;977      */
;;;978    void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
000000  2100              MOVS     r1,#0
;;;979    {
;;;980      /* Set the default configuration */
;;;981      TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
000002  8001              STRH     r1,[r0,#0]
;;;982      TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
000004  8041              STRH     r1,[r0,#2]
;;;983      TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
000006  8081              STRH     r1,[r0,#4]
;;;984      TIM_OCInitStruct->TIM_Pulse = 0x00000000;
000008  6081              STR      r1,[r0,#8]
;;;985      TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
00000a  8181              STRH     r1,[r0,#0xc]
;;;986      TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
00000c  81c1              STRH     r1,[r0,#0xe]
;;;987      TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
00000e  8201              STRH     r1,[r0,#0x10]
;;;988      TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
000010  8241              STRH     r1,[r0,#0x12]
;;;989    }
000012  4770              BX       lr
;;;990    
                          ENDP


                          AREA ||i.TIM_PWMIConfig||, CODE, READONLY, ALIGN=1

                  TIM_PWMIConfig PROC
;;;1974     */
;;;1975   void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
000000  e92d41f0          PUSH     {r4-r8,lr}
;;;1976   {
000004  4607              MOV      r7,r0
000006  460c              MOV      r4,r1
;;;1977     uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
000008  2500              MOVS     r5,#0
;;;1978     uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
00000a  2601              MOVS     r6,#1
;;;1979   
;;;1980     /* Check the parameters */
;;;1981     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;1982   
;;;1983     /* Select the Opposite Input Polarity */
;;;1984     if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
00000c  8861              LDRH     r1,[r4,#2]
00000e  2900              CMP      r1,#0
000010  d100              BNE      |L65.20|
;;;1985     {
;;;1986       icoppositepolarity = TIM_ICPolarity_Falling;
000012  2502              MOVS     r5,#2
                  |L65.20|
;;;1987     }
;;;1988     else
;;;1989     {
;;;1990       icoppositepolarity = TIM_ICPolarity_Rising;
;;;1991     }
;;;1992     /* Select the Opposite Input */
;;;1993     if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
000014  88a2              LDRH     r2,[r4,#4]
000016  2a01              CMP      r2,#1
000018  d100              BNE      |L65.28|
;;;1994     {
;;;1995       icoppositeselection = TIM_ICSelection_IndirectTI;
00001a  2602              MOVS     r6,#2
                  |L65.28|
;;;1996     }
;;;1997     else
;;;1998     {
;;;1999       icoppositeselection = TIM_ICSelection_DirectTI;
;;;2000     }
;;;2001     if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
00001c  8820              LDRH     r0,[r4,#0]
;;;2002     {
;;;2003       /* TI1 Configuration */
;;;2004       TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
00001e  8923              LDRH     r3,[r4,#8]
000020  b190              CBZ      r0,|L65.72|
;;;2005                  TIM_ICInitStruct->TIM_ICFilter);
;;;2006       /* Set the Input Capture Prescaler value */
;;;2007       TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
;;;2008       /* TI2 Configuration */
;;;2009       TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
;;;2010       /* Set the Input Capture Prescaler value */
;;;2011       TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
;;;2012     }
;;;2013     else
;;;2014     { 
;;;2015       /* TI2 Configuration */
;;;2016       TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
000022  4638              MOV      r0,r7
000024  f7fffffe          BL       TI2_Config
;;;2017                  TIM_ICInitStruct->TIM_ICFilter);
;;;2018       /* Set the Input Capture Prescaler value */
;;;2019       TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000028  88e1              LDRH     r1,[r4,#6]
00002a  4638              MOV      r0,r7
00002c  f7fffffe          BL       TIM_SetIC2Prescaler
;;;2020       /* TI1 Configuration */
;;;2021       TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
000030  8923              LDRH     r3,[r4,#8]
000032  4632              MOV      r2,r6
000034  4629              MOV      r1,r5
000036  4638              MOV      r0,r7
000038  f7fffffe          BL       TI1_Config
;;;2022       /* Set the Input Capture Prescaler value */
;;;2023       TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00003c  88e1              LDRH     r1,[r4,#6]
00003e  4638              MOV      r0,r7
000040  e8bd41f0          POP      {r4-r8,lr}
000044  f7ffbffe          B.W      TIM_SetIC1Prescaler
                  |L65.72|
000048  4638              MOV      r0,r7                 ;2004
00004a  f7fffffe          BL       TI1_Config
00004e  88e1              LDRH     r1,[r4,#6]            ;2007
000050  4638              MOV      r0,r7                 ;2007
000052  f7fffffe          BL       TIM_SetIC1Prescaler
000056  8923              LDRH     r3,[r4,#8]            ;2009
000058  4632              MOV      r2,r6                 ;2009
00005a  4629              MOV      r1,r5                 ;2009
00005c  4638              MOV      r0,r7                 ;2009
00005e  f7fffffe          BL       TI2_Config
000062  88e1              LDRH     r1,[r4,#6]            ;2011
000064  4638              MOV      r0,r7                 ;2011
000066  e8bd41f0          POP      {r4-r8,lr}            ;2011
00006a  f7ffbffe          B.W      TIM_SetIC2Prescaler
;;;2024     }
;;;2025   }
;;;2026   
                          ENDP


                          AREA ||i.TIM_PrescalerConfig||, CODE, READONLY, ALIGN=1

                  TIM_PrescalerConfig PROC
;;;359      */
;;;360    void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
000000  8501              STRH     r1,[r0,#0x28]
;;;361    {
;;;362      /* Check the parameters */
;;;363      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;364      assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
;;;365      /* Set the Prescaler value */
;;;366      TIMx->PSC = Prescaler;
;;;367      /* Set or reset the UG Bit */
;;;368      TIMx->EGR = TIM_PSCReloadMode;
000002  8282              STRH     r2,[r0,#0x14]
;;;369    }
000004  4770              BX       lr
;;;370    
                          ENDP


                          AREA ||i.TIM_RemapConfig||, CODE, READONLY, ALIGN=1

                  TIM_RemapConfig PROC
;;;3172     */
;;;3173   void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
000000  f8a01050          STRH     r1,[r0,#0x50]
;;;3174   {
;;;3175    /* Check the parameters */
;;;3176     assert_param(IS_TIM_LIST6_PERIPH(TIMx));
;;;3177     assert_param(IS_TIM_REMAP(TIM_Remap));
;;;3178   
;;;3179     /* Set the Timer remapping configuration */
;;;3180     TIMx->OR =  TIM_Remap;
;;;3181   }
000004  4770              BX       lr
;;;3182   /**
                          ENDP


                          AREA ||i.TIM_SelectCCDMA||, CODE, READONLY, ALIGN=1

                  TIM_SelectCCDMA PROC
;;;2643     */
;;;2644   void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;2645   {
000002  d004              BEQ      |L68.14|
;;;2646     /* Check the parameters */
;;;2647     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2648     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2649   
;;;2650     if (NewState != DISABLE)
;;;2651     {
;;;2652       /* Set the CCDS Bit */
;;;2653       TIMx->CR2 |= TIM_CR2_CCDS;
000004  8881              LDRH     r1,[r0,#4]
000006  f0410108          ORR      r1,r1,#8
00000a  8081              STRH     r1,[r0,#4]
;;;2654     }
;;;2655     else
;;;2656     {
;;;2657       /* Reset the CCDS Bit */
;;;2658       TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS;
;;;2659     }
;;;2660   }
00000c  4770              BX       lr
                  |L68.14|
00000e  8881              LDRH     r1,[r0,#4]            ;2658
000010  f0210108          BIC      r1,r1,#8              ;2658
000014  8081              STRH     r1,[r0,#4]            ;2658
000016  4770              BX       lr
;;;2661   /**
                          ENDP


                          AREA ||i.TIM_SelectCOM||, CODE, READONLY, ALIGN=1

                  TIM_SelectCOM PROC
;;;2289     */
;;;2290   void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;2291   {
000002  d004              BEQ      |L69.14|
;;;2292     /* Check the parameters */
;;;2293     assert_param(IS_TIM_LIST4_PERIPH(TIMx));
;;;2294     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2295   
;;;2296     if (NewState != DISABLE)
;;;2297     {
;;;2298       /* Set the COM Bit */
;;;2299       TIMx->CR2 |= TIM_CR2_CCUS;
000004  8881              LDRH     r1,[r0,#4]
000006  f0410104          ORR      r1,r1,#4
00000a  8081              STRH     r1,[r0,#4]
;;;2300     }
;;;2301     else
;;;2302     {
;;;2303       /* Reset the COM Bit */
;;;2304       TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS;
;;;2305     }
;;;2306   }
00000c  4770              BX       lr
                  |L69.14|
00000e  8881              LDRH     r1,[r0,#4]            ;2304
000010  f0210104          BIC      r1,r1,#4              ;2304
000014  8081              STRH     r1,[r0,#4]            ;2304
000016  4770              BX       lr
;;;2307   
                          ENDP


                          AREA ||i.TIM_SelectHallSensor||, CODE, READONLY, ALIGN=1

                  TIM_SelectHallSensor PROC
;;;3121     */
;;;3122   void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;3123   {
000002  d004              BEQ      |L70.14|
;;;3124     /* Check the parameters */
;;;3125     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;3126     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;3127   
;;;3128     if (NewState != DISABLE)
;;;3129     {
;;;3130       /* Set the TI1S Bit */
;;;3131       TIMx->CR2 |= TIM_CR2_TI1S;
000004  8881              LDRH     r1,[r0,#4]
000006  f0410180          ORR      r1,r1,#0x80
00000a  8081              STRH     r1,[r0,#4]
;;;3132     }
;;;3133     else
;;;3134     {
;;;3135       /* Reset the TI1S Bit */
;;;3136       TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S;
;;;3137     }
;;;3138   }
00000c  4770              BX       lr
                  |L70.14|
00000e  8881              LDRH     r1,[r0,#4]            ;3136
000010  f0210180          BIC      r1,r1,#0x80           ;3136
000014  8081              STRH     r1,[r0,#4]            ;3136
000016  4770              BX       lr
;;;3139   /**
                          ENDP


                          AREA ||i.TIM_SelectInputTrigger||, CODE, READONLY, ALIGN=1

                  TIM_SelectInputTrigger PROC
;;;2891     */
;;;2892   void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
000000  8902              LDRH     r2,[r0,#8]
;;;2893   {
;;;2894     uint16_t tmpsmcr = 0;
;;;2895   
;;;2896     /* Check the parameters */
;;;2897     assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 
;;;2898     assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
;;;2899   
;;;2900     /* Get the TIMx SMCR register value */
;;;2901     tmpsmcr = TIMx->SMCR;
;;;2902   
;;;2903     /* Reset the TS Bits */
;;;2904     tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
000002  f0220270          BIC      r2,r2,#0x70
;;;2905   
;;;2906     /* Set the Input Trigger source */
;;;2907     tmpsmcr |= TIM_InputTriggerSource;
000006  430a              ORRS     r2,r2,r1
;;;2908   
;;;2909     /* Write to TIMx SMCR */
;;;2910     TIMx->SMCR = tmpsmcr;
000008  8102              STRH     r2,[r0,#8]
;;;2911   }
00000a  4770              BX       lr
;;;2912   
                          ENDP


                          AREA ||i.TIM_SelectMasterSlaveMode||, CODE, READONLY, ALIGN=1

                  TIM_SelectMasterSlaveMode PROC
;;;2981     */
;;;2982   void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
000000  8902              LDRH     r2,[r0,#8]
;;;2983   {
;;;2984     /* Check the parameters */
;;;2985     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;2986     assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
;;;2987   
;;;2988     /* Reset the MSM Bit */
;;;2989     TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM;
000002  f0220280          BIC      r2,r2,#0x80
000006  8102              STRH     r2,[r0,#8]
;;;2990     
;;;2991     /* Set or Reset the MSM Bit */
;;;2992     TIMx->SMCR |= TIM_MasterSlaveMode;
000008  8902              LDRH     r2,[r0,#8]
00000a  430a              ORRS     r2,r2,r1
00000c  8102              STRH     r2,[r0,#8]
;;;2993   }
00000e  4770              BX       lr
;;;2994   
                          ENDP


                          AREA ||i.TIM_SelectOCxM||, CODE, READONLY, ALIGN=1

                  TIM_SelectOCxM PROC
;;;1013     */
;;;1014   void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
000000  b530              PUSH     {r4,r5,lr}
;;;1015   {
;;;1016     uint32_t tmp = 0;
;;;1017     uint16_t tmp1 = 0;
;;;1018   
;;;1019     /* Check the parameters */
;;;1020     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;1021     assert_param(IS_TIM_CHANNEL(TIM_Channel));
;;;1022     assert_param(IS_TIM_OCM(TIM_OCMode));
;;;1023   
;;;1024     tmp = (uint32_t) TIMx;
;;;1025     tmp += CCMR_OFFSET;
000002  f1000318          ADD      r3,r0,#0x18
;;;1026   
;;;1027     tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
000006  2401              MOVS     r4,#1
000008  408c              LSLS     r4,r4,r1
;;;1028   
;;;1029     /* Disable the Channel: Reset the CCxE Bit */
;;;1030     TIMx->CCER &= (uint16_t) ~tmp1;
00000a  8c05              LDRH     r5,[r0,#0x20]
00000c  43a5              BICS     r5,r5,r4
00000e  8405              STRH     r5,[r0,#0x20]
;;;1031   
;;;1032     if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
000010  2900              CMP      r1,#0
000012  d012              BEQ      |L73.58|
000014  2908              CMP      r1,#8
000016  d010              BEQ      |L73.58|
;;;1033     {
;;;1034       tmp += (TIM_Channel>>1);
;;;1035   
;;;1036       /* Reset the OCxM bits in the CCMRx register */
;;;1037       *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK;
;;;1038      
;;;1039       /* Configure the OCxM bits in the CCMRx register */
;;;1040       *(__IO uint32_t *) tmp |= TIM_OCMode;
;;;1041     }
;;;1042     else
;;;1043     {
;;;1044       tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
000018  1f09              SUBS     r1,r1,#4
00001a  f3c1004e          UBFX     r0,r1,#1,#15
00001e  4418              ADD      r0,r0,r3
;;;1045   
;;;1046       /* Reset the OCxM bits in the CCMRx register */
;;;1047       *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK;
000020  6801              LDR      r1,[r0,#0]
000022  f64873ff          MOV      r3,#0x8fff
000026  4019              ANDS     r1,r1,r3
000028  6001              STR      r1,[r0,#0]
;;;1048       
;;;1049       /* Configure the OCxM bits in the CCMRx register */
;;;1050       *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
00002a  6801              LDR      r1,[r0,#0]
00002c  f64f73ff          MOV      r3,#0xffff
000030  ea032202          AND      r2,r3,r2,LSL #8
000034  4311              ORRS     r1,r1,r2
000036  6001              STR      r1,[r0,#0]
;;;1051     }
;;;1052   }
000038  bd30              POP      {r4,r5,pc}
                  |L73.58|
00003a  eb030051          ADD      r0,r3,r1,LSR #1       ;1034
00003e  6801              LDR      r1,[r0,#0]            ;1037
000040  f64f738f          MOV      r3,#0xff8f            ;1037
000044  4019              ANDS     r1,r1,r3              ;1037
000046  6001              STR      r1,[r0,#0]            ;1037
000048  6801              LDR      r1,[r0,#0]            ;1040
00004a  4311              ORRS     r1,r1,r2              ;1040
00004c  6001              STR      r1,[r0,#0]            ;1040
00004e  bd30              POP      {r4,r5,pc}
;;;1053   
                          ENDP


                          AREA ||i.TIM_SelectOnePulseMode||, CODE, READONLY, ALIGN=1

                  TIM_SelectOnePulseMode PROC
;;;548      */
;;;549    void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
000000  8802              LDRH     r2,[r0,#0]
;;;550    {
;;;551      /* Check the parameters */
;;;552      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;553      assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
;;;554    
;;;555      /* Reset the OPM Bit */
;;;556      TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM;
000002  f0220208          BIC      r2,r2,#8
000006  8002              STRH     r2,[r0,#0]
;;;557    
;;;558      /* Configure the OPM Mode */
;;;559      TIMx->CR1 |= TIM_OPMode;
000008  8802              LDRH     r2,[r0,#0]
00000a  430a              ORRS     r2,r2,r1
00000c  8002              STRH     r2,[r0,#0]
;;;560    }
00000e  4770              BX       lr
;;;561    
                          ENDP


                          AREA ||i.TIM_SelectOutputTrigger||, CODE, READONLY, ALIGN=1

                  TIM_SelectOutputTrigger PROC
;;;2934     */
;;;2935   void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
000000  8882              LDRH     r2,[r0,#4]
;;;2936   {
;;;2937     /* Check the parameters */
;;;2938     assert_param(IS_TIM_LIST5_PERIPH(TIMx));
;;;2939     assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
;;;2940   
;;;2941     /* Reset the MMS Bits */
;;;2942     TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS;
000002  f0220270          BIC      r2,r2,#0x70
000006  8082              STRH     r2,[r0,#4]
;;;2943     /* Select the TRGO source */
;;;2944     TIMx->CR2 |=  TIM_TRGOSource;
000008  8882              LDRH     r2,[r0,#4]
00000a  430a              ORRS     r2,r2,r1
00000c  8082              STRH     r2,[r0,#4]
;;;2945   }
00000e  4770              BX       lr
;;;2946   
                          ENDP


                          AREA ||i.TIM_SelectSlaveMode||, CODE, READONLY, ALIGN=1

                  TIM_SelectSlaveMode PROC
;;;2958     */
;;;2959   void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
000000  8902              LDRH     r2,[r0,#8]
;;;2960   {
;;;2961     /* Check the parameters */
;;;2962     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;2963     assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
;;;2964   
;;;2965     /* Reset the SMS Bits */
;;;2966     TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
000002  f0220207          BIC      r2,r2,#7
000006  8102              STRH     r2,[r0,#8]
;;;2967   
;;;2968     /* Select the Slave Mode */
;;;2969     TIMx->SMCR |= TIM_SlaveMode;
000008  8902              LDRH     r2,[r0,#8]
00000a  430a              ORRS     r2,r2,r1
00000c  8102              STRH     r2,[r0,#8]
;;;2970   }
00000e  4770              BX       lr
;;;2971   
                          ENDP


                          AREA ||i.TIM_SetAutoreload||, CODE, READONLY, ALIGN=1

                  TIM_SetAutoreload PROC
;;;423      */
;;;424    void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
000000  62c1              STR      r1,[r0,#0x2c]
;;;425    {
;;;426      /* Check the parameters */
;;;427      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;428      
;;;429      /* Set the Autoreload Register value */
;;;430      TIMx->ARR = Autoreload;
;;;431    }
000002  4770              BX       lr
;;;432    
                          ENDP


                          AREA ||i.TIM_SetClockDivision||, CODE, READONLY, ALIGN=1

                  TIM_SetClockDivision PROC
;;;571      */
;;;572    void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
000000  8802              LDRH     r2,[r0,#0]
;;;573    {
;;;574      /* Check the parameters */
;;;575      assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;576      assert_param(IS_TIM_CKD_DIV(TIM_CKD));
;;;577    
;;;578      /* Reset the CKD Bits */
;;;579      TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD);
000002  f4227240          BIC      r2,r2,#0x300
000006  8002              STRH     r2,[r0,#0]
;;;580    
;;;581      /* Set the CKD value */
;;;582      TIMx->CR1 |= TIM_CKD;
000008  8802              LDRH     r2,[r0,#0]
00000a  430a              ORRS     r2,r2,r1
00000c  8002              STRH     r2,[r0,#0]
;;;583    }
00000e  4770              BX       lr
;;;584    
                          ENDP


                          AREA ||i.TIM_SetCompare1||, CODE, READONLY, ALIGN=1

                  TIM_SetCompare1 PROC
;;;1059     */
;;;1060   void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
000000  6341              STR      r1,[r0,#0x34]
;;;1061   {
;;;1062     /* Check the parameters */
;;;1063     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;1064   
;;;1065     /* Set the Capture Compare1 Register value */
;;;1066     TIMx->CCR1 = Compare1;
;;;1067   }
000002  4770              BX       lr
;;;1068   
                          ENDP


                          AREA ||i.TIM_SetCompare2||, CODE, READONLY, ALIGN=1

                  TIM_SetCompare2 PROC
;;;1075     */
;;;1076   void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
000000  6381              STR      r1,[r0,#0x38]
;;;1077   {
;;;1078     /* Check the parameters */
;;;1079     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;1080   
;;;1081     /* Set the Capture Compare2 Register value */
;;;1082     TIMx->CCR2 = Compare2;
;;;1083   }
000002  4770              BX       lr
;;;1084   
                          ENDP


                          AREA ||i.TIM_SetCompare3||, CODE, READONLY, ALIGN=1

                  TIM_SetCompare3 PROC
;;;1090     */
;;;1091   void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
000000  63c1              STR      r1,[r0,#0x3c]
;;;1092   {
;;;1093     /* Check the parameters */
;;;1094     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1095   
;;;1096     /* Set the Capture Compare3 Register value */
;;;1097     TIMx->CCR3 = Compare3;
;;;1098   }
000002  4770              BX       lr
;;;1099   
                          ENDP


                          AREA ||i.TIM_SetCompare4||, CODE, READONLY, ALIGN=1

                  TIM_SetCompare4 PROC
;;;1105     */
;;;1106   void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
000000  6401              STR      r1,[r0,#0x40]
;;;1107   {
;;;1108     /* Check the parameters */
;;;1109     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1110   
;;;1111     /* Set the Capture Compare4 Register value */
;;;1112     TIMx->CCR4 = Compare4;
;;;1113   }
000002  4770              BX       lr
;;;1114   
                          ENDP


                          AREA ||i.TIM_SetCounter||, CODE, READONLY, ALIGN=1

                  TIM_SetCounter PROC
;;;408      */
;;;409    void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
000000  6241              STR      r1,[r0,#0x24]
;;;410    {
;;;411      /* Check the parameters */
;;;412       assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;413    
;;;414      /* Set the Counter Register value */
;;;415      TIMx->CNT = Counter;
;;;416    }
000002  4770              BX       lr
;;;417    
                          ENDP


                          AREA ||i.TIM_SetIC1Prescaler||, CODE, READONLY, ALIGN=1

                  TIM_SetIC1Prescaler PROC
;;;2094     */
;;;2095   void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
000000  8b02              LDRH     r2,[r0,#0x18]
;;;2096   {
;;;2097     /* Check the parameters */
;;;2098     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;2099     assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
;;;2100   
;;;2101     /* Reset the IC1PSC Bits */
;;;2102     TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC;
000002  f022020c          BIC      r2,r2,#0xc
000006  8302              STRH     r2,[r0,#0x18]
;;;2103   
;;;2104     /* Set the IC1PSC value */
;;;2105     TIMx->CCMR1 |= TIM_ICPSC;
000008  8b02              LDRH     r2,[r0,#0x18]
00000a  430a              ORRS     r2,r2,r1
00000c  8302              STRH     r2,[r0,#0x18]
;;;2106   }
00000e  4770              BX       lr
;;;2107   
                          ENDP


                          AREA ||i.TIM_SetIC2Prescaler||, CODE, READONLY, ALIGN=1

                  TIM_SetIC2Prescaler PROC
;;;2119     */
;;;2120   void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
000000  8b02              LDRH     r2,[r0,#0x18]
;;;2121   {
;;;2122     /* Check the parameters */
;;;2123     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;2124     assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
;;;2125   
;;;2126     /* Reset the IC2PSC Bits */
;;;2127     TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC;
000002  f4226240          BIC      r2,r2,#0xc00
000006  8302              STRH     r2,[r0,#0x18]
;;;2128   
;;;2129     /* Set the IC2PSC value */
;;;2130     TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
000008  8b02              LDRH     r2,[r0,#0x18]
00000a  f64f73ff          MOV      r3,#0xffff
00000e  ea032101          AND      r1,r3,r1,LSL #8
000012  430a              ORRS     r2,r2,r1
000014  8302              STRH     r2,[r0,#0x18]
;;;2131   }
000016  4770              BX       lr
;;;2132   
                          ENDP


                          AREA ||i.TIM_SetIC3Prescaler||, CODE, READONLY, ALIGN=1

                  TIM_SetIC3Prescaler PROC
;;;2143     */
;;;2144   void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
000000  8b82              LDRH     r2,[r0,#0x1c]
;;;2145   {
;;;2146     /* Check the parameters */
;;;2147     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2148     assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
;;;2149   
;;;2150     /* Reset the IC3PSC Bits */
;;;2151     TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC;
000002  f022020c          BIC      r2,r2,#0xc
000006  8382              STRH     r2,[r0,#0x1c]
;;;2152   
;;;2153     /* Set the IC3PSC value */
;;;2154     TIMx->CCMR2 |= TIM_ICPSC;
000008  8b82              LDRH     r2,[r0,#0x1c]
00000a  430a              ORRS     r2,r2,r1
00000c  8382              STRH     r2,[r0,#0x1c]
;;;2155   }
00000e  4770              BX       lr
;;;2156   
                          ENDP


                          AREA ||i.TIM_SetIC4Prescaler||, CODE, READONLY, ALIGN=1

                  TIM_SetIC4Prescaler PROC
;;;2167     */
;;;2168   void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
000000  8b82              LDRH     r2,[r0,#0x1c]
;;;2169   {  
;;;2170     /* Check the parameters */
;;;2171     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2172     assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
;;;2173   
;;;2174     /* Reset the IC4PSC Bits */
;;;2175     TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC;
000002  f4226240          BIC      r2,r2,#0xc00
000006  8382              STRH     r2,[r0,#0x1c]
;;;2176   
;;;2177     /* Set the IC4PSC value */
;;;2178     TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
000008  8b82              LDRH     r2,[r0,#0x1c]
00000a  f64f73ff          MOV      r3,#0xffff
00000e  ea032101          AND      r1,r3,r1,LSL #8
000012  430a              ORRS     r2,r2,r1
000014  8382              STRH     r2,[r0,#0x1c]
;;;2179   }
000016  4770              BX       lr
;;;2180   /**
                          ENDP


                          AREA ||i.TIM_TIxExternalClockConfig||, CODE, READONLY, ALIGN=1

                  TIM_TIxExternalClockConfig PROC
;;;2733     */
;;;2734   void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
000000  b570              PUSH     {r4-r6,lr}
;;;2735                                   uint16_t TIM_ICPolarity, uint16_t ICFilter)
;;;2736   {
000002  460d              MOV      r5,r1
000004  4604              MOV      r4,r0
000006  4611              MOV      r1,r2
;;;2737     /* Check the parameters */
;;;2738     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;2739     assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
;;;2740     assert_param(IS_TIM_IC_FILTER(ICFilter));
;;;2741   
;;;2742     /* Configure the Timer Input Clock Source */
;;;2743     if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
000008  2d60              CMP      r5,#0x60
00000a  d00c              BEQ      |L88.38|
;;;2744     {
;;;2745       TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
;;;2746     }
;;;2747     else
;;;2748     {
;;;2749       TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
00000c  2201              MOVS     r2,#1
00000e  4620              MOV      r0,r4
000010  f7fffffe          BL       TI1_Config
                  |L88.20|
;;;2750     }
;;;2751     /* Select the Trigger source */
;;;2752     TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
000014  4629              MOV      r1,r5
000016  4620              MOV      r0,r4
000018  f7fffffe          BL       TIM_SelectInputTrigger
;;;2753     /* Select the External clock mode1 */
;;;2754     TIMx->SMCR |= TIM_SlaveMode_External1;
00001c  8920              LDRH     r0,[r4,#8]
00001e  f0400007          ORR      r0,r0,#7
000022  8120              STRH     r0,[r4,#8]
;;;2755   }
000024  bd70              POP      {r4-r6,pc}
                  |L88.38|
000026  2201              MOVS     r2,#1                 ;2745
000028  4620              MOV      r0,r4                 ;2745
00002a  f7fffffe          BL       TI2_Config
00002e  e7f1              B        |L88.20|
;;;2756   
                          ENDP


                          AREA ||i.TIM_TimeBaseInit||, CODE, READONLY, ALIGN=2

                  TIM_TimeBaseInit PROC
;;;287      */
;;;288    void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
000000  b530              PUSH     {r4,r5,lr}
;;;289    {
;;;290      uint16_t tmpcr1 = 0;
;;;291    
;;;292      /* Check the parameters */
;;;293      assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
;;;294      assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
;;;295      assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
;;;296    
;;;297      tmpcr1 = TIMx->CR1;  
000002  8802              LDRH     r2,[r0,#0]
;;;298    
;;;299      if((TIMx == TIM1) || (TIMx == TIM8)||
000004  4c16              LDR      r4,|L89.96|
000006  4d17              LDR      r5,|L89.100|
000008  42a0              CMP      r0,r4
00000a  d00d              BEQ      |L89.40|
00000c  42a8              CMP      r0,r5
00000e  d00b              BEQ      |L89.40|
;;;300         (TIMx == TIM2) || (TIMx == TIM3)||
000010  f1b04f80          CMP      r0,#0x40000000
000014  d008              BEQ      |L89.40|
000016  4b14              LDR      r3,|L89.104|
000018  4298              CMP      r0,r3
00001a  d005              BEQ      |L89.40|
;;;301         (TIMx == TIM4) || (TIMx == TIM5)) 
00001c  4b13              LDR      r3,|L89.108|
00001e  4298              CMP      r0,r3
000020  d002              BEQ      |L89.40|
000022  4b13              LDR      r3,|L89.112|
000024  4298              CMP      r0,r3
000026  d103              BNE      |L89.48|
                  |L89.40|
;;;302      {
;;;303        /* Select the Counter Mode */
;;;304        tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS));
000028  f0220370          BIC      r3,r2,#0x70
;;;305        tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
00002c  884a              LDRH     r2,[r1,#2]
00002e  431a              ORRS     r2,r2,r3
                  |L89.48|
;;;306      }
;;;307     
;;;308      if((TIMx != TIM6) && (TIMx != TIM7))
000030  4b10              LDR      r3,|L89.116|
000032  4298              CMP      r0,r3
000034  d006              BEQ      |L89.68|
000036  4b10              LDR      r3,|L89.120|
000038  4298              CMP      r0,r3
00003a  d003              BEQ      |L89.68|
;;;309      {
;;;310        /* Set the clock division */
;;;311        tmpcr1 &=  (uint16_t)(~TIM_CR1_CKD);
00003c  f4227340          BIC      r3,r2,#0x300
;;;312        tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
000040  890a              LDRH     r2,[r1,#8]
000042  431a              ORRS     r2,r2,r3
                  |L89.68|
;;;313      }
;;;314    
;;;315      TIMx->CR1 = tmpcr1;
000044  8002              STRH     r2,[r0,#0]
;;;316    
;;;317      /* Set the Autoreload value */
;;;318      TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
000046  684a              LDR      r2,[r1,#4]
000048  62c2              STR      r2,[r0,#0x2c]
;;;319     
;;;320      /* Set the Prescaler value */
;;;321      TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
00004a  880a              LDRH     r2,[r1,#0]
00004c  8502              STRH     r2,[r0,#0x28]
;;;322        
;;;323      if ((TIMx == TIM1) || (TIMx == TIM8))  
00004e  42a0              CMP      r0,r4
000050  d001              BEQ      |L89.86|
000052  42a8              CMP      r0,r5
000054  d101              BNE      |L89.90|
                  |L89.86|
;;;324      {
;;;325        /* Set the Repetition Counter value */
;;;326        TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
000056  7a89              LDRB     r1,[r1,#0xa]
000058  8601              STRH     r1,[r0,#0x30]
                  |L89.90|
;;;327      }
;;;328    
;;;329      /* Generate an update event to reload the Prescaler 
;;;330         and the repetition counter(only for TIM1 and TIM8) value immediately */
;;;331      TIMx->EGR = TIM_PSCReloadMode_Immediate;          
00005a  2101              MOVS     r1,#1
00005c  8281              STRH     r1,[r0,#0x14]
;;;332    }
00005e  bd30              POP      {r4,r5,pc}
;;;333    
                          ENDP

                  |L89.96|
                          DCD      0x40010000
                  |L89.100|
                          DCD      0x40010400
                  |L89.104|
                          DCD      0x40000400
                  |L89.108|
                          DCD      0x40000800
                  |L89.112|
                          DCD      0x40000c00
                  |L89.116|
                          DCD      0x40001000
                  |L89.120|
                          DCD      0x40001400

                          AREA ||i.TIM_TimeBaseStructInit||, CODE, READONLY, ALIGN=1

                  TIM_TimeBaseStructInit PROC
;;;339      */
;;;340    void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
000000  f04f31ff          MOV      r1,#0xffffffff
;;;341    {
;;;342      /* Set the default configuration */
;;;343      TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
000004  6041              STR      r1,[r0,#4]
;;;344      TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
000006  2100              MOVS     r1,#0
000008  8001              STRH     r1,[r0,#0]
;;;345      TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
00000a  8101              STRH     r1,[r0,#8]
;;;346      TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
00000c  8041              STRH     r1,[r0,#2]
;;;347      TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
00000e  7281              STRB     r1,[r0,#0xa]
;;;348    }
000010  4770              BX       lr
;;;349    
                          ENDP


                          AREA ||i.TIM_UpdateDisableConfig||, CODE, READONLY, ALIGN=1

                  TIM_UpdateDisableConfig PROC
;;;467      */
;;;468    void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;469    {
000002  d004              BEQ      |L91.14|
;;;470      /* Check the parameters */
;;;471      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;472      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;473    
;;;474      if (NewState != DISABLE)
;;;475      {
;;;476        /* Set the Update Disable Bit */
;;;477        TIMx->CR1 |= TIM_CR1_UDIS;
000004  8801              LDRH     r1,[r0,#0]
000006  f0410102          ORR      r1,r1,#2
00000a  8001              STRH     r1,[r0,#0]
;;;478      }
;;;479      else
;;;480      {
;;;481        /* Reset the Update Disable Bit */
;;;482        TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS;
;;;483      }
;;;484    }
00000c  4770              BX       lr
                  |L91.14|
00000e  8801              LDRH     r1,[r0,#0]            ;482
000010  f0210102          BIC      r1,r1,#2              ;482
000014  8001              STRH     r1,[r0,#0]            ;482
000016  4770              BX       lr
;;;485    
                          ENDP


                          AREA ||i.TIM_UpdateRequestConfig||, CODE, READONLY, ALIGN=1

                  TIM_UpdateRequestConfig PROC
;;;496      */
;;;497    void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
000000  2900              CMP      r1,#0
;;;498    {
000002  d004              BEQ      |L92.14|
;;;499      /* Check the parameters */
;;;500      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;501      assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
;;;502    
;;;503      if (TIM_UpdateSource != TIM_UpdateSource_Global)
;;;504      {
;;;505        /* Set the URS Bit */
;;;506        TIMx->CR1 |= TIM_CR1_URS;
000004  8801              LDRH     r1,[r0,#0]
000006  f0410104          ORR      r1,r1,#4
00000a  8001              STRH     r1,[r0,#0]
;;;507      }
;;;508      else
;;;509      {
;;;510        /* Reset the URS Bit */
;;;511        TIMx->CR1 &= (uint16_t)~TIM_CR1_URS;
;;;512      }
;;;513    }
00000c  4770              BX       lr
                  |L92.14|
00000e  8801              LDRH     r1,[r0,#0]            ;511
000010  f0210104          BIC      r1,r1,#4              ;511
000014  8001              STRH     r1,[r0,#0]            ;511
000016  4770              BX       lr
;;;514    
                          ENDP


;*** Start embedded assembler ***

#line 1 "..\\..\\Libraries\\STM32F4xx_StdPeriph_Driver\\src\\stm32f4xx_tim.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f4xx_tim_c_c458916b____REV16|
#line 129 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h"
|__asm___15_stm32f4xx_tim_c_c458916b____REV16| PROC
#line 130

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f4xx_tim_c_c458916b____REVSH|
#line 144
|__asm___15_stm32f4xx_tim_c_c458916b____REVSH| PROC
#line 145

 revsh r0, r0
 bx lr
	ENDP
	AREA ||.rrx_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f4xx_tim_c_c458916b____RRX|
#line 300
|__asm___15_stm32f4xx_tim_c_c458916b____RRX| PROC
#line 301

 rrx r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***