AGV / agv_shengyiPPxiaoche · Files

; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\flash\obj\stm32f4xx_rcc.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\stm32f4xx_rcc.d --cpu=Cortex-M4.fp --apcs=interwork -O1 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Include -I..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\uCOS-III\uC-CPU -I..\..\uCOS-III\uC-LIB -I..\..\uCOS-III\uCOS-III\Ports -I..\..\uCOS-III\uCOS-III\Source -I..\..\uCOS-III\uC-CPU\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uC-LIB\Ports\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uCOS-III\Ports\ARM-Cortex-M4\Generic\RealView -I..\..\User -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\libapp -I..\..\RL-ARM\Config -I..\..\RL-ARM\Driver -I..\..\RL-ARM\RL-RTX\inc -I..\..\User\bsp\BSP -I..\..\RL-ARM\RL-CAN -I..\..\Libraries\DSP_LIB\Include -I..\..\MODBUS\modbus\rtu -I..\..\MODBUS\BARE\port -I..\..\MODBUS\modbus\include -I..\..\User\bsp\BSP -I..\..\PLC -I..\..\Avoid -I..\..\User\parameter -I..\..\User\LaserMotionCtr -I..\..\User\W5100S -I..\..\User\bsp -I..\..\User\CHASSIS -I..\..\User\CONTROLFUNCTION -I..\..\User\DATAUPDATE -I..\..\User\HARAWARE -I..\..\User\MOTORDRIVER -I..\..\User\NAVAGATION -I..\..\User\PLATFORM -I..\..\User\SENSOR -I.\RTE\_Flash -IC:\Users\YDJ\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include -IC:\Users\YDJ\AppData\Local\Arm\Packs\Keil\STM32F4xx_DFP\2.13.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include -D__UVISION_VERSION=527 -D_RTE_ -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -D__RTX -D__FPU_USED=1 --omf_browse=.\flash\obj\stm32f4xx_rcc.crf ..\..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rcc.c]
                          THUMB

                          AREA ||i.RCC_AHB1PeriphClockCmd||, CODE, READONLY, ALIGN=2

                  RCC_AHB1PeriphClockCmd PROC
;;;1789     */
;;;1790   void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
000000  4a05              LDR      r2,|L1.24|
;;;1791   {
;;;1792     /* Check the parameters */
;;;1793     assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
;;;1794   
;;;1795     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1796     if (NewState != DISABLE)
000002  2900              CMP      r1,#0
000004  d003              BEQ      |L1.14|
;;;1797     {
;;;1798       RCC->AHB1ENR |= RCC_AHB1Periph;
000006  6811              LDR      r1,[r2,#0]
000008  4301              ORRS     r1,r1,r0
00000a  6011              STR      r1,[r2,#0]
;;;1799     }
;;;1800     else
;;;1801     {
;;;1802       RCC->AHB1ENR &= ~RCC_AHB1Periph;
;;;1803     }
;;;1804   }
00000c  4770              BX       lr
                  |L1.14|
00000e  6811              LDR      r1,[r2,#0]            ;1802
000010  4381              BICS     r1,r1,r0              ;1802
000012  6011              STR      r1,[r2,#0]            ;1802
000014  4770              BX       lr
;;;1805   
                          ENDP

000016  0000              DCW      0x0000
                  |L1.24|
                          DCD      0x40023830

                          AREA ||i.RCC_AHB1PeriphClockLPModeCmd||, CODE, READONLY, ALIGN=2

                  RCC_AHB1PeriphClockLPModeCmd PROC
;;;2195     */
;;;2196   void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
000000  4a05              LDR      r2,|L2.24|
;;;2197   {
;;;2198     /* Check the parameters */
;;;2199     assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
;;;2200     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2201     if (NewState != DISABLE)
000002  2900              CMP      r1,#0
000004  d003              BEQ      |L2.14|
;;;2202     {
;;;2203       RCC->AHB1LPENR |= RCC_AHB1Periph;
000006  6811              LDR      r1,[r2,#0]
000008  4301              ORRS     r1,r1,r0
00000a  6011              STR      r1,[r2,#0]
;;;2204     }
;;;2205     else
;;;2206     {
;;;2207       RCC->AHB1LPENR &= ~RCC_AHB1Periph;
;;;2208     }
;;;2209   }
00000c  4770              BX       lr
                  |L2.14|
00000e  6811              LDR      r1,[r2,#0]            ;2207
000010  4381              BICS     r1,r1,r0              ;2207
000012  6011              STR      r1,[r2,#0]            ;2207
000014  4770              BX       lr
;;;2210   
                          ENDP

000016  0000              DCW      0x0000
                  |L2.24|
                          DCD      0x40023850

                          AREA ||i.RCC_AHB1PeriphResetCmd||, CODE, READONLY, ALIGN=2

                  RCC_AHB1PeriphResetCmd PROC
;;;1995     */
;;;1996   void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
000000  4a05              LDR      r2,|L3.24|
;;;1997   {
;;;1998     /* Check the parameters */
;;;1999     assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
;;;2000     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2001   
;;;2002     if (NewState != DISABLE)
000002  2900              CMP      r1,#0
000004  d003              BEQ      |L3.14|
;;;2003     {
;;;2004       RCC->AHB1RSTR |= RCC_AHB1Periph;
000006  6811              LDR      r1,[r2,#0]
000008  4301              ORRS     r1,r1,r0
00000a  6011              STR      r1,[r2,#0]
;;;2005     }
;;;2006     else
;;;2007     {
;;;2008       RCC->AHB1RSTR &= ~RCC_AHB1Periph;
;;;2009     }
;;;2010   }
00000c  4770              BX       lr
                  |L3.14|
00000e  6811              LDR      r1,[r2,#0]            ;2008
000010  4381              BICS     r1,r1,r0              ;2008
000012  6011              STR      r1,[r2,#0]            ;2008
000014  4770              BX       lr
;;;2011   
                          ENDP

000016  0000              DCW      0x0000
                  |L3.24|
                          DCD      0x40023810

                          AREA ||i.RCC_AHB2PeriphClockCmd||, CODE, READONLY, ALIGN=2

                  RCC_AHB2PeriphClockCmd PROC
;;;1821     */
;;;1822   void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
000000  4a05              LDR      r2,|L4.24|
;;;1823   {
;;;1824     /* Check the parameters */
;;;1825     assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
;;;1826     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1827   
;;;1828     if (NewState != DISABLE)
000002  2900              CMP      r1,#0
000004  d003              BEQ      |L4.14|
;;;1829     {
;;;1830       RCC->AHB2ENR |= RCC_AHB2Periph;
000006  6811              LDR      r1,[r2,#0]
000008  4301              ORRS     r1,r1,r0
00000a  6011              STR      r1,[r2,#0]
;;;1831     }
;;;1832     else
;;;1833     {
;;;1834       RCC->AHB2ENR &= ~RCC_AHB2Periph;
;;;1835     }
;;;1836   }
00000c  4770              BX       lr
                  |L4.14|
00000e  6811              LDR      r1,[r2,#0]            ;1834
000010  4381              BICS     r1,r1,r0              ;1834
000012  6011              STR      r1,[r2,#0]            ;1834
000014  4770              BX       lr
;;;1837   
                          ENDP

000016  0000              DCW      0x0000
                  |L4.24|
                          DCD      0x40023834

                          AREA ||i.RCC_AHB2PeriphClockLPModeCmd||, CODE, READONLY, ALIGN=2

                  RCC_AHB2PeriphClockLPModeCmd PROC
;;;2227     */
;;;2228   void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
000000  4a05              LDR      r2,|L5.24|
;;;2229   {
;;;2230     /* Check the parameters */
;;;2231     assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
;;;2232     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2233     if (NewState != DISABLE)
000002  2900              CMP      r1,#0
000004  d003              BEQ      |L5.14|
;;;2234     {
;;;2235       RCC->AHB2LPENR |= RCC_AHB2Periph;
000006  6811              LDR      r1,[r2,#0]
000008  4301              ORRS     r1,r1,r0
00000a  6011              STR      r1,[r2,#0]
;;;2236     }
;;;2237     else
;;;2238     {
;;;2239       RCC->AHB2LPENR &= ~RCC_AHB2Periph;
;;;2240     }
;;;2241   }
00000c  4770              BX       lr
                  |L5.14|
00000e  6811              LDR      r1,[r2,#0]            ;2239
000010  4381              BICS     r1,r1,r0              ;2239
000012  6011              STR      r1,[r2,#0]            ;2239
000014  4770              BX       lr
;;;2242   
                          ENDP

000016  0000              DCW      0x0000
                  |L5.24|
                          DCD      0x40023854

                          AREA ||i.RCC_AHB2PeriphResetCmd||, CODE, READONLY, ALIGN=2

                  RCC_AHB2PeriphResetCmd PROC
;;;2024     */
;;;2025   void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
000000  4a05              LDR      r2,|L6.24|
;;;2026   {
;;;2027     /* Check the parameters */
;;;2028     assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
;;;2029     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2030   
;;;2031     if (NewState != DISABLE)
000002  2900              CMP      r1,#0
000004  d003              BEQ      |L6.14|
;;;2032     {
;;;2033       RCC->AHB2RSTR |= RCC_AHB2Periph;
000006  6811              LDR      r1,[r2,#0]
000008  4301              ORRS     r1,r1,r0
00000a  6011              STR      r1,[r2,#0]
;;;2034     }
;;;2035     else
;;;2036     {
;;;2037       RCC->AHB2RSTR &= ~RCC_AHB2Periph;
;;;2038     }
;;;2039   }
00000c  4770              BX       lr
                  |L6.14|
00000e  6811              LDR      r1,[r2,#0]            ;2037
000010  4381              BICS     r1,r1,r0              ;2037
000012  6011              STR      r1,[r2,#0]            ;2037
000014  4770              BX       lr
;;;2040   
                          ENDP

000016  0000              DCW      0x0000
                  |L6.24|
                          DCD      0x40023814

                          AREA ||i.RCC_AHB3PeriphClockCmd||, CODE, READONLY, ALIGN=2

                  RCC_AHB3PeriphClockCmd PROC
;;;1851     */
;;;1852   void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
000000  4a05              LDR      r2,|L7.24|
;;;1853   {
;;;1854     /* Check the parameters */
;;;1855     assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));  
;;;1856     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1857   
;;;1858     if (NewState != DISABLE)
000002  2900              CMP      r1,#0
000004  d003              BEQ      |L7.14|
;;;1859     {
;;;1860       RCC->AHB3ENR |= RCC_AHB3Periph;
000006  6811              LDR      r1,[r2,#0]
000008  4301              ORRS     r1,r1,r0
00000a  6011              STR      r1,[r2,#0]
;;;1861     }
;;;1862     else
;;;1863     {
;;;1864       RCC->AHB3ENR &= ~RCC_AHB3Periph;
;;;1865     }
;;;1866   }
00000c  4770              BX       lr
                  |L7.14|
00000e  6811              LDR      r1,[r2,#0]            ;1864
000010  4381              BICS     r1,r1,r0              ;1864
000012  6011              STR      r1,[r2,#0]            ;1864
000014  4770              BX       lr
;;;1867   #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx */
                          ENDP

000016  0000              DCW      0x0000
                  |L7.24|
                          DCD      0x40023838

                          AREA ||i.RCC_AHB3PeriphClockLPModeCmd||, CODE, READONLY, ALIGN=2

                  RCC_AHB3PeriphClockLPModeCmd PROC
;;;2257     */
;;;2258   void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
000000  4a05              LDR      r2,|L8.24|
;;;2259   {
;;;2260     /* Check the parameters */
;;;2261     assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
;;;2262     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2263     if (NewState != DISABLE)
000002  2900              CMP      r1,#0
000004  d003              BEQ      |L8.14|
;;;2264     {
;;;2265       RCC->AHB3LPENR |= RCC_AHB3Periph;
000006  6811              LDR      r1,[r2,#0]
000008  4301              ORRS     r1,r1,r0
00000a  6011              STR      r1,[r2,#0]
;;;2266     }
;;;2267     else
;;;2268     {
;;;2269       RCC->AHB3LPENR &= ~RCC_AHB3Periph;
;;;2270     }
;;;2271   }
00000c  4770              BX       lr
                  |L8.14|
00000e  6811              LDR      r1,[r2,#0]            ;2269
000010  4381              BICS     r1,r1,r0              ;2269
000012  6011              STR      r1,[r2,#0]            ;2269
000014  4770              BX       lr
;;;2272   #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx */
                          ENDP

000016  0000              DCW      0x0000
                  |L8.24|
                          DCD      0x40023858

                          AREA ||i.RCC_AHB3PeriphResetCmd||, CODE, READONLY, ALIGN=2

                  RCC_AHB3PeriphResetCmd PROC
;;;2051     */
;;;2052   void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
000000  4a05              LDR      r2,|L9.24|
;;;2053   {
;;;2054     /* Check the parameters */
;;;2055     assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
;;;2056     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2057   
;;;2058     if (NewState != DISABLE)
000002  2900              CMP      r1,#0
000004  d003              BEQ      |L9.14|
;;;2059     {
;;;2060       RCC->AHB3RSTR |= RCC_AHB3Periph;
000006  6811              LDR      r1,[r2,#0]
000008  4301              ORRS     r1,r1,r0
00000a  6011              STR      r1,[r2,#0]
;;;2061     }
;;;2062     else
;;;2063     {
;;;2064       RCC->AHB3RSTR &= ~RCC_AHB3Periph;
;;;2065     }
;;;2066   }
00000c  4770              BX       lr
                  |L9.14|
00000e  6811              LDR      r1,[r2,#0]            ;2064
000010  4381              BICS     r1,r1,r0              ;2064
000012  6011              STR      r1,[r2,#0]            ;2064
000014  4770              BX       lr
;;;2067   #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx */
                          ENDP

000016  0000              DCW      0x0000
                  |L9.24|
                          DCD      0x40023818

                          AREA ||i.RCC_APB1PeriphClockCmd||, CODE, READONLY, ALIGN=2

                  RCC_APB1PeriphClockCmd PROC
;;;1907     */
;;;1908   void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
000000  4a05              LDR      r2,|L10.24|
;;;1909   {
;;;1910     /* Check the parameters */
;;;1911     assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));  
;;;1912     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1913   
;;;1914     if (NewState != DISABLE)
000002  2900              CMP      r1,#0
000004  d003              BEQ      |L10.14|
;;;1915     {
;;;1916       RCC->APB1ENR |= RCC_APB1Periph;
000006  6811              LDR      r1,[r2,#0]
000008  4301              ORRS     r1,r1,r0
00000a  6011              STR      r1,[r2,#0]
;;;1917     }
;;;1918     else
;;;1919     {
;;;1920       RCC->APB1ENR &= ~RCC_APB1Periph;
;;;1921     }
;;;1922   }
00000c  4770              BX       lr
                  |L10.14|
00000e  6811              LDR      r1,[r2,#0]            ;1920
000010  4381              BICS     r1,r1,r0              ;1920
000012  6011              STR      r1,[r2,#0]            ;1920
000014  4770              BX       lr
;;;1923   
                          ENDP

000016  0000              DCW      0x0000
                  |L10.24|
                          DCD      0x40023840

                          AREA ||i.RCC_APB1PeriphClockLPModeCmd||, CODE, READONLY, ALIGN=2

                  RCC_APB1PeriphClockLPModeCmd PROC
;;;2313     */
;;;2314   void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
000000  4a05              LDR      r2,|L11.24|
;;;2315   {
;;;2316     /* Check the parameters */
;;;2317     assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
;;;2318     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2319     if (NewState != DISABLE)
000002  2900              CMP      r1,#0
000004  d003              BEQ      |L11.14|
;;;2320     {
;;;2321       RCC->APB1LPENR |= RCC_APB1Periph;
000006  6811              LDR      r1,[r2,#0]
000008  4301              ORRS     r1,r1,r0
00000a  6011              STR      r1,[r2,#0]
;;;2322     }
;;;2323     else
;;;2324     {
;;;2325       RCC->APB1LPENR &= ~RCC_APB1Periph;
;;;2326     }
;;;2327   }
00000c  4770              BX       lr
                  |L11.14|
00000e  6811              LDR      r1,[r2,#0]            ;2325
000010  4381              BICS     r1,r1,r0              ;2325
000012  6011              STR      r1,[r2,#0]            ;2325
000014  4770              BX       lr
;;;2328   
                          ENDP

000016  0000              DCW      0x0000
                  |L11.24|
                          DCD      0x40023860

                          AREA ||i.RCC_APB1PeriphResetCmd||, CODE, READONLY, ALIGN=2

                  RCC_APB1PeriphResetCmd PROC
;;;2104     */
;;;2105   void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
000000  4a05              LDR      r2,|L12.24|
;;;2106   {
;;;2107     /* Check the parameters */
;;;2108     assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
;;;2109     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2110     if (NewState != DISABLE)
000002  2900              CMP      r1,#0
000004  d003              BEQ      |L12.14|
;;;2111     {
;;;2112       RCC->APB1RSTR |= RCC_APB1Periph;
000006  6811              LDR      r1,[r2,#0]
000008  4301              ORRS     r1,r1,r0
00000a  6011              STR      r1,[r2,#0]
;;;2113     }
;;;2114     else
;;;2115     {
;;;2116       RCC->APB1RSTR &= ~RCC_APB1Periph;
;;;2117     }
;;;2118   }
00000c  4770              BX       lr
                  |L12.14|
00000e  6811              LDR      r1,[r2,#0]            ;2116
000010  4381              BICS     r1,r1,r0              ;2116
000012  6011              STR      r1,[r2,#0]            ;2116
000014  4770              BX       lr
;;;2119   
                          ENDP

000016  0000              DCW      0x0000
                  |L12.24|
                          DCD      0x40023820

                          AREA ||i.RCC_APB2PeriphClockCmd||, CODE, READONLY, ALIGN=2

                  RCC_APB2PeriphClockCmd PROC
;;;1953     */
;;;1954   void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
000000  4a05              LDR      r2,|L13.24|
;;;1955   {
;;;1956     /* Check the parameters */
;;;1957     assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
;;;1958     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1959   
;;;1960     if (NewState != DISABLE)
000002  2900              CMP      r1,#0
000004  d003              BEQ      |L13.14|
;;;1961     {
;;;1962       RCC->APB2ENR |= RCC_APB2Periph;
000006  6811              LDR      r1,[r2,#0]
000008  4301              ORRS     r1,r1,r0
00000a  6011              STR      r1,[r2,#0]
;;;1963     }
;;;1964     else
;;;1965     {
;;;1966       RCC->APB2ENR &= ~RCC_APB2Periph;
;;;1967     }
;;;1968   }
00000c  4770              BX       lr
                  |L13.14|
00000e  6811              LDR      r1,[r2,#0]            ;1966
000010  4381              BICS     r1,r1,r0              ;1966
000012  6011              STR      r1,[r2,#0]            ;1966
000014  4770              BX       lr
;;;1969   
                          ENDP

000016  0000              DCW      0x0000
                  |L13.24|
                          DCD      0x40023844

                          AREA ||i.RCC_APB2PeriphClockLPModeCmd||, CODE, READONLY, ALIGN=2

                  RCC_APB2PeriphClockLPModeCmd PROC
;;;2359     */
;;;2360   void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
000000  4a05              LDR      r2,|L14.24|
;;;2361   {
;;;2362     /* Check the parameters */
;;;2363     assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
;;;2364     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2365     if (NewState != DISABLE)
000002  2900              CMP      r1,#0
000004  d003              BEQ      |L14.14|
;;;2366     {
;;;2367       RCC->APB2LPENR |= RCC_APB2Periph;
000006  6811              LDR      r1,[r2,#0]
000008  4301              ORRS     r1,r1,r0
00000a  6011              STR      r1,[r2,#0]
;;;2368     }
;;;2369     else
;;;2370     {
;;;2371       RCC->APB2LPENR &= ~RCC_APB2Periph;
;;;2372     }
;;;2373   }
00000c  4770              BX       lr
                  |L14.14|
00000e  6811              LDR      r1,[r2,#0]            ;2371
000010  4381              BICS     r1,r1,r0              ;2371
000012  6011              STR      r1,[r2,#0]            ;2371
000014  4770              BX       lr
;;;2374   
                          ENDP

000016  0000              DCW      0x0000
                  |L14.24|
                          DCD      0x40023864

                          AREA ||i.RCC_APB2PeriphResetCmd||, CODE, READONLY, ALIGN=2

                  RCC_APB2PeriphResetCmd PROC
;;;2146     */
;;;2147   void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
000000  4a05              LDR      r2,|L15.24|
;;;2148   {
;;;2149     /* Check the parameters */
;;;2150     assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
;;;2151     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2152     if (NewState != DISABLE)
000002  2900              CMP      r1,#0
000004  d003              BEQ      |L15.14|
;;;2153     {
;;;2154       RCC->APB2RSTR |= RCC_APB2Periph;
000006  6811              LDR      r1,[r2,#0]
000008  4301              ORRS     r1,r1,r0
00000a  6011              STR      r1,[r2,#0]
;;;2155     }
;;;2156     else
;;;2157     {
;;;2158       RCC->APB2RSTR &= ~RCC_APB2Periph;
;;;2159     }
;;;2160   }
00000c  4770              BX       lr
                  |L15.14|
00000e  6811              LDR      r1,[r2,#0]            ;2158
000010  4381              BICS     r1,r1,r0              ;2158
000012  6011              STR      r1,[r2,#0]            ;2158
000014  4770              BX       lr
;;;2161   
                          ENDP

000016  0000              DCW      0x0000
                  |L15.24|
                          DCD      0x40023824

                          AREA ||i.RCC_AdjustHSICalibrationValue||, CODE, READONLY, ALIGN=2

                  RCC_AdjustHSICalibrationValue PROC
;;;317      */
;;;318    void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
000000  4a03              LDR      r2,|L16.16|
;;;319    {
;;;320      uint32_t tmpreg = 0;
;;;321      /* Check the parameters */
;;;322      assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
;;;323    
;;;324      tmpreg = RCC->CR;
000002  6811              LDR      r1,[r2,#0]
;;;325    
;;;326      /* Clear HSITRIM[4:0] bits */
;;;327      tmpreg &= ~RCC_CR_HSITRIM;
000004  f02101f8          BIC      r1,r1,#0xf8
;;;328    
;;;329      /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
;;;330      tmpreg |= (uint32_t)HSICalibrationValue << 3;
000008  ea4100c0          ORR      r0,r1,r0,LSL #3
;;;331    
;;;332      /* Store the new value */
;;;333      RCC->CR = tmpreg;
00000c  6010              STR      r0,[r2,#0]
;;;334    }
00000e  4770              BX       lr
;;;335    
                          ENDP

                  |L16.16|
                          DCD      0x40023800

                          AREA ||i.RCC_BackupResetCmd||, CODE, READONLY, ALIGN=2

                  RCC_BackupResetCmd PROC
;;;1449     */
;;;1450   void RCC_BackupResetCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L17.8|
;;;1451   {
;;;1452     /* Check the parameters */
;;;1453     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1454     *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
000002  6008              STR      r0,[r1,#0]
;;;1455   }
000004  4770              BX       lr
;;;1456   
                          ENDP

000006  0000              DCW      0x0000
                  |L17.8|
                          DCD      0x42470e40

                          AREA ||i.RCC_ClearFlag||, CODE, READONLY, ALIGN=2

                  RCC_ClearFlag PROC
;;;2663     */
;;;2664   void RCC_ClearFlag(void)
000000  4802              LDR      r0,|L18.12|
;;;2665   {
;;;2666     /* Set RMVF bit to clear the reset flags */
;;;2667     RCC->CSR |= RCC_CSR_RMVF;
000002  6801              LDR      r1,[r0,#0]
000004  f0417180          ORR      r1,r1,#0x1000000
000008  6001              STR      r1,[r0,#0]
;;;2668   }
00000a  4770              BX       lr
;;;2669   
                          ENDP

                  |L18.12|
                          DCD      0x40023874

                          AREA ||i.RCC_ClearITPendingBit||, CODE, READONLY, ALIGN=2

                  RCC_ClearITPendingBit PROC
;;;2717     */
;;;2718   void RCC_ClearITPendingBit(uint8_t RCC_IT)
000000  4901              LDR      r1,|L19.8|
;;;2719   {
;;;2720     /* Check the parameters */
;;;2721     assert_param(IS_RCC_CLEAR_IT(RCC_IT));
;;;2722   
;;;2723     /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
;;;2724        pending bits */
;;;2725     *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
000002  7008              STRB     r0,[r1,#0]
;;;2726   }
000004  4770              BX       lr
;;;2727   
                          ENDP

000006  0000              DCW      0x0000
                  |L19.8|
                          DCD      0x4002380e

                          AREA ||i.RCC_ClockSecuritySystemCmd||, CODE, READONLY, ALIGN=2

                  RCC_ClockSecuritySystemCmd PROC
;;;819      */
;;;820    void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L20.8|
;;;821    {
;;;822      /* Check the parameters */
;;;823      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;824      *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
000002  64c8              STR      r0,[r1,#0x4c]
;;;825    }
000004  4770              BX       lr
;;;826    
                          ENDP

000006  0000              DCW      0x0000
                  |L20.8|
                          DCD      0x42470000

                          AREA ||i.RCC_DeInit||, CODE, READONLY, ALIGN=2

                  RCC_DeInit PROC
;;;212      */
;;;213    void RCC_DeInit(void)
000000  4810              LDR      r0,|L21.68|
;;;214    {
;;;215      /* Set HSION bit */
;;;216      RCC->CR |= (uint32_t)0x00000001;
000002  6801              LDR      r1,[r0,#0]
000004  f0410101          ORR      r1,r1,#1
000008  6001              STR      r1,[r0,#0]
;;;217    
;;;218      /* Reset CFGR register */
;;;219      RCC->CFGR = 0x00000000;
00000a  4a0e              LDR      r2,|L21.68|
00000c  2100              MOVS     r1,#0
00000e  3208              ADDS     r2,r2,#8
000010  6011              STR      r1,[r2,#0]
;;;220    
;;;221      /* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42/43xxx devices) bits */
;;;222      RCC->CR &= (uint32_t)0xEAF6FFFF;
000012  6802              LDR      r2,[r0,#0]
000014  4b0c              LDR      r3,|L21.72|
000016  401a              ANDS     r2,r2,r3
000018  6002              STR      r2,[r0,#0]
;;;223    
;;;224      /* Reset PLLCFGR register */
;;;225      RCC->PLLCFGR = 0x24003010;
00001a  1d03              ADDS     r3,r0,#4
00001c  4a0b              LDR      r2,|L21.76|
00001e  601a              STR      r2,[r3,#0]
;;;226    
;;;227      /* Reset PLLI2SCFGR register */
;;;228      RCC->PLLI2SCFGR = 0x20003000;
000020  4b08              LDR      r3,|L21.68|
000022  4a0b              LDR      r2,|L21.80|
000024  3384              ADDS     r3,r3,#0x84
000026  601a              STR      r2,[r3,#0]
;;;229    
;;;230      /* Reset PLLSAICFGR register, only available for STM32F42/43xxx devices */
;;;231      RCC->PLLSAICFGR = 0x24003000;
000028  4a08              LDR      r2,|L21.76|
00002a  3a10              SUBS     r2,r2,#0x10
00002c  1d1b              ADDS     r3,r3,#4
00002e  601a              STR      r2,[r3,#0]
;;;232     
;;;233      /* Reset HSEBYP bit */
;;;234      RCC->CR &= (uint32_t)0xFFFBFFFF;
000030  6802              LDR      r2,[r0,#0]
000032  f4222280          BIC      r2,r2,#0x40000
000036  6002              STR      r2,[r0,#0]
;;;235    
;;;236      /* Disable all interrupts */
;;;237      RCC->CIR = 0x00000000;
000038  4802              LDR      r0,|L21.68|
00003a  300c              ADDS     r0,r0,#0xc
00003c  6001              STR      r1,[r0,#0]
;;;238    
;;;239      /* Disable Timers clock prescalers selection, only available for STM32F42/43xxx devices */
;;;240      RCC->DCKCFGR = 0x00000000; 
00003e  1d18              ADDS     r0,r3,#4
000040  6001              STR      r1,[r0,#0]
;;;241    }
000042  4770              BX       lr
;;;242    
                          ENDP

                  |L21.68|
                          DCD      0x40023800
                  |L21.72|
                          DCD      0xeaf6ffff
                  |L21.76|
                          DCD      0x24003010
                  |L21.80|
                          DCD      0x20003000

                          AREA ||i.RCC_GetClocksFreq||, CODE, READONLY, ALIGN=2

                  RCC_GetClocksFreq PROC
;;;1247     */
;;;1248   void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
000000  b570              PUSH     {r4-r6,lr}
;;;1249   {
;;;1250     uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
;;;1251   #if defined(STM32F446xx)  
;;;1252     uint32_t pllr = 2;
;;;1253   #endif /* STM32F446xx */
;;;1254     
;;;1255     /* Get SYSCLK source -------------------------------------------------------*/
;;;1256     tmp = RCC->CFGR & RCC_CFGR_SWS;
000002  4b24              LDR      r3,|L22.148|
000004  6819              LDR      r1,[r3,#0]
000006  f001010c          AND      r1,r1,#0xc
;;;1257     
;;;1258     switch (tmp)
;;;1259     {
;;;1260     case 0x00:  /* HSI used as system clock source */
;;;1261       RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
00000a  4c23              LDR      r4,|L22.152|
00000c  2900              CMP      r1,#0                 ;1258
00000e  d01e              BEQ      |L22.78|
;;;1262       break;
;;;1263     case 0x04:  /* HSE used as system clock  source */
;;;1264       RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
000010  1066              ASRS     r6,r4,#1
000012  2904              CMP      r1,#4                 ;1258
000014  d01d              BEQ      |L22.82|
000016  2908              CMP      r1,#8                 ;1258
000018  d01d              BEQ      |L22.86|
;;;1265       break;
;;;1266     case 0x08:  /* PLL P used as system clock  source */
;;;1267       
;;;1268       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
;;;1269       SYSCLK = PLL_VCO / PLLP
;;;1270       */    
;;;1271       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
;;;1272       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
;;;1273       
;;;1274       if (pllsource != 0)
;;;1275       {
;;;1276         /* HSE used as PLL clock source */
;;;1277         pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
;;;1278       }
;;;1279       else
;;;1280       {
;;;1281         /* HSI used as PLL clock source */
;;;1282         pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
;;;1283       }
;;;1284       
;;;1285       pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
;;;1286       RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
;;;1287       break;
;;;1288   
;;;1289   #if defined(STM32F446xx)
;;;1290     case 0x0C:  /* PLL R used as system clock  source */
;;;1291       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
;;;1292       SYSCLK = PLL_VCO / PLLR
;;;1293       */    
;;;1294       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
;;;1295       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
;;;1296       
;;;1297       if (pllsource != 0)
;;;1298       {
;;;1299         /* HSE used as PLL clock source */
;;;1300         pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
;;;1301       }
;;;1302       else
;;;1303       {
;;;1304         /* HSI used as PLL clock source */
;;;1305         pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
;;;1306       }
;;;1307       
;;;1308       pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2;
;;;1309       RCC_Clocks->SYSCLK_Frequency = pllvco/pllr;    
;;;1310       break;
;;;1311   #endif /* STM32F446xx */
;;;1312       
;;;1313     default:
;;;1314       RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
00001a  6004              STR      r4,[r0,#0]
                  |L22.28|
;;;1315       break;
;;;1316     }
;;;1317     /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
;;;1318     
;;;1319     /* Get HCLK prescaler */
;;;1320     tmp = RCC->CFGR & RCC_CFGR_HPRE;
00001c  6819              LDR      r1,[r3,#0]
00001e  f00101f0          AND      r1,r1,#0xf0
;;;1321     tmp = tmp >> 4;
000022  0909              LSRS     r1,r1,#4
;;;1322     presc = APBAHBPrescTable[tmp];
000024  4a1d              LDR      r2,|L22.156|
000026  5c54              LDRB     r4,[r2,r1]
;;;1323     /* HCLK clock frequency */
;;;1324     RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
000028  6801              LDR      r1,[r0,#0]
00002a  40e1              LSRS     r1,r1,r4
00002c  6041              STR      r1,[r0,#4]
;;;1325   
;;;1326     /* Get PCLK1 prescaler */
;;;1327     tmp = RCC->CFGR & RCC_CFGR_PPRE1;
00002e  681c              LDR      r4,[r3,#0]
000030  f40454e0          AND      r4,r4,#0x1c00
;;;1328     tmp = tmp >> 10;
000034  0aa4              LSRS     r4,r4,#10
;;;1329     presc = APBAHBPrescTable[tmp];
000036  5d14              LDRB     r4,[r2,r4]
;;;1330     /* PCLK1 clock frequency */
;;;1331     RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
000038  fa21f404          LSR      r4,r1,r4
00003c  6084              STR      r4,[r0,#8]
;;;1332   
;;;1333     /* Get PCLK2 prescaler */
;;;1334     tmp = RCC->CFGR & RCC_CFGR_PPRE2;
00003e  681b              LDR      r3,[r3,#0]
000040  f4034360          AND      r3,r3,#0xe000
;;;1335     tmp = tmp >> 13;
000044  0b5b              LSRS     r3,r3,#13
;;;1336     presc = APBAHBPrescTable[tmp];
000046  5cd2              LDRB     r2,[r2,r3]
;;;1337     /* PCLK2 clock frequency */
;;;1338     RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
000048  40d1              LSRS     r1,r1,r2
00004a  60c1              STR      r1,[r0,#0xc]
00004c  bd70              POP      {r4-r6,pc}            ;1262
                  |L22.78|
00004e  6004              STR      r4,[r0,#0]            ;1261
000050  e7e4              B        |L22.28|
                  |L22.82|
000052  6006              STR      r6,[r0,#0]            ;1264
000054  e7e2              B        |L22.28|
                  |L22.86|
000056  4a0f              LDR      r2,|L22.148|
000058  1f12              SUBS     r2,r2,#4              ;1271
00005a  6811              LDR      r1,[r2,#0]            ;1271
00005c  f3c15580          UBFX     r5,r1,#22,#1          ;1271
000060  6811              LDR      r1,[r2,#0]            ;1272
000062  f001013f          AND      r1,r1,#0x3f           ;1272
000066  b135              CBZ      r5,|L22.118|
000068  fbb6f1f1          UDIV     r1,r6,r1              ;1277
00006c  6814              LDR      r4,[r2,#0]            ;1277
00006e  f3c41488          UBFX     r4,r4,#6,#9           ;1277
000072  4361              MULS     r1,r4,r1              ;1277
000074  e005              B        |L22.130|
                  |L22.118|
000076  fbb4f1f1          UDIV     r1,r4,r1              ;1282
00007a  6814              LDR      r4,[r2,#0]            ;1282
00007c  f3c41488          UBFX     r4,r4,#6,#9           ;1282
000080  4361              MULS     r1,r4,r1              ;1282
                  |L22.130|
000082  6812              LDR      r2,[r2,#0]            ;1285
000084  f3c24201          UBFX     r2,r2,#16,#2          ;1285
000088  1c52              ADDS     r2,r2,#1              ;1285
00008a  0052              LSLS     r2,r2,#1              ;1285
00008c  fbb1f1f2          UDIV     r1,r1,r2              ;1286
000090  6001              STR      r1,[r0,#0]            ;1286
000092  e7c3              B        |L22.28|
;;;1339   }
;;;1340   
                          ENDP

                  |L22.148|
                          DCD      0x40023808
                  |L22.152|
                          DCD      0x00f42400
                  |L22.156|
                          DCD      ||.data||

                          AREA ||i.RCC_GetFlagStatus||, CODE, READONLY, ALIGN=2

                  RCC_GetFlagStatus PROC
;;;2618     */
;;;2619   FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
000000  4602              MOV      r2,r0
;;;2620   {
;;;2621     uint32_t tmp = 0;
;;;2622     uint32_t statusreg = 0;
;;;2623     FlagStatus bitstatus = RESET;
000002  2000              MOVS     r0,#0
;;;2624   
;;;2625     /* Check the parameters */
;;;2626     assert_param(IS_RCC_FLAG(RCC_FLAG));
;;;2627   
;;;2628     /* Get the RCC register index */
;;;2629     tmp = RCC_FLAG >> 5;
000004  0951              LSRS     r1,r2,#5
;;;2630     if (tmp == 1)               /* The flag to check is in CR register */
000006  2901              CMP      r1,#1
000008  d00b              BEQ      |L23.34|
;;;2631     {
;;;2632       statusreg = RCC->CR;
;;;2633     }
;;;2634     else if (tmp == 2)          /* The flag to check is in BDCR register */
00000a  2902              CMP      r1,#2
00000c  d00d              BEQ      |L23.42|
;;;2635     {
;;;2636       statusreg = RCC->BDCR;
;;;2637     }
;;;2638     else                       /* The flag to check is in CSR register */
;;;2639     {
;;;2640       statusreg = RCC->CSR;
00000e  4909              LDR      r1,|L23.52|
000010  6809              LDR      r1,[r1,#0]
                  |L23.18|
;;;2641     }
;;;2642   
;;;2643     /* Get the flag position */
;;;2644     tmp = RCC_FLAG & FLAG_MASK;
000012  f002021f          AND      r2,r2,#0x1f
;;;2645     if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
000016  2301              MOVS     r3,#1
000018  4093              LSLS     r3,r3,r2
00001a  420b              TST      r3,r1
00001c  d000              BEQ      |L23.32|
;;;2646     {
;;;2647       bitstatus = SET;
00001e  2001              MOVS     r0,#1
                  |L23.32|
;;;2648     }
;;;2649     else
;;;2650     {
;;;2651       bitstatus = RESET;
;;;2652     }
;;;2653     /* Return the flag status */
;;;2654     return bitstatus;
;;;2655   }
000020  4770              BX       lr
                  |L23.34|
000022  4904              LDR      r1,|L23.52|
000024  3974              SUBS     r1,r1,#0x74           ;2632
000026  6809              LDR      r1,[r1,#0]            ;2632
000028  e7f3              B        |L23.18|
                  |L23.42|
00002a  4902              LDR      r1,|L23.52|
00002c  1f09              SUBS     r1,r1,#4              ;2636
00002e  6809              LDR      r1,[r1,#0]            ;2636
000030  e7ef              B        |L23.18|
;;;2656   
                          ENDP

000032  0000              DCW      0x0000
                  |L23.52|
                          DCD      0x40023874

                          AREA ||i.RCC_GetITStatus||, CODE, READONLY, ALIGN=2

                  RCC_GetITStatus PROC
;;;2683     */
;;;2684   ITStatus RCC_GetITStatus(uint8_t RCC_IT)
000000  4601              MOV      r1,r0
;;;2685   {
;;;2686     ITStatus bitstatus = RESET;
000002  2000              MOVS     r0,#0
;;;2687   
;;;2688     /* Check the parameters */
;;;2689     assert_param(IS_RCC_GET_IT(RCC_IT));
;;;2690   
;;;2691     /* Check the status of the specified RCC interrupt */
;;;2692     if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
000004  4a02              LDR      r2,|L24.16|
000006  6812              LDR      r2,[r2,#0]
000008  420a              TST      r2,r1
00000a  d000              BEQ      |L24.14|
;;;2693     {
;;;2694       bitstatus = SET;
00000c  2001              MOVS     r0,#1
                  |L24.14|
;;;2695     }
;;;2696     else
;;;2697     {
;;;2698       bitstatus = RESET;
;;;2699     }
;;;2700     /* Return the RCC_IT status */
;;;2701     return  bitstatus;
;;;2702   }
00000e  4770              BX       lr
;;;2703   
                          ENDP

                  |L24.16|
                          DCD      0x4002380c

                          AREA ||i.RCC_GetSYSCLKSource||, CODE, READONLY, ALIGN=2

                  RCC_GetSYSCLKSource PROC
;;;1107     */
;;;1108   uint8_t RCC_GetSYSCLKSource(void)
000000  4802              LDR      r0,|L25.12|
;;;1109   {
;;;1110     return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
000002  6800              LDR      r0,[r0,#0]
000004  f000000c          AND      r0,r0,#0xc
;;;1111   }
000008  4770              BX       lr
;;;1112   
                          ENDP

00000a  0000              DCW      0x0000
                  |L25.12|
                          DCD      0x40023808

                          AREA ||i.RCC_HCLKConfig||, CODE, READONLY, ALIGN=2

                  RCC_HCLKConfig PROC
;;;1132     */
;;;1133   void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
000000  4a03              LDR      r2,|L26.16|
;;;1134   {
;;;1135     uint32_t tmpreg = 0;
;;;1136     
;;;1137     /* Check the parameters */
;;;1138     assert_param(IS_RCC_HCLK(RCC_SYSCLK));
;;;1139   
;;;1140     tmpreg = RCC->CFGR;
000002  6811              LDR      r1,[r2,#0]
;;;1141   
;;;1142     /* Clear HPRE[3:0] bits */
;;;1143     tmpreg &= ~RCC_CFGR_HPRE;
000004  f02101f0          BIC      r1,r1,#0xf0
;;;1144   
;;;1145     /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
;;;1146     tmpreg |= RCC_SYSCLK;
000008  4301              ORRS     r1,r1,r0
;;;1147   
;;;1148     /* Store the new value */
;;;1149     RCC->CFGR = tmpreg;
00000a  6011              STR      r1,[r2,#0]
;;;1150   }
00000c  4770              BX       lr
;;;1151   
                          ENDP

00000e  0000              DCW      0x0000
                  |L26.16|
                          DCD      0x40023808

                          AREA ||i.RCC_HSEConfig||, CODE, READONLY, ALIGN=2

                  RCC_HSEConfig PROC
;;;262      */
;;;263    void RCC_HSEConfig(uint8_t RCC_HSE)
000000  4902              LDR      r1,|L27.12|
;;;264    {
;;;265      /* Check the parameters */
;;;266      assert_param(IS_RCC_HSE(RCC_HSE));
;;;267    
;;;268      /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
;;;269      *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
000002  2200              MOVS     r2,#0
000004  700a              STRB     r2,[r1,#0]
;;;270    
;;;271      /* Set the new HSE configuration -------------------------------------------*/
;;;272      *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
000006  7008              STRB     r0,[r1,#0]
;;;273    }
000008  4770              BX       lr
;;;274    
                          ENDP

00000a  0000              DCW      0x0000
                  |L27.12|
                          DCD      0x40023802

                          AREA ||i.RCC_HSICmd||, CODE, READONLY, ALIGN=2

                  RCC_HSICmd PROC
;;;353      */
;;;354    void RCC_HSICmd(FunctionalState NewState)
000000  4901              LDR      r1,|L28.8|
;;;355    {
;;;356      /* Check the parameters */
;;;357      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;358    
;;;359      *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
000002  6008              STR      r0,[r1,#0]
;;;360    }
000004  4770              BX       lr
;;;361    
                          ENDP

000006  0000              DCW      0x0000
                  |L28.8|
                          DCD      0x42470000

                          AREA ||i.RCC_I2SCLKConfig||, CODE, READONLY, ALIGN=2

                  RCC_I2SCLKConfig PROC
;;;1548     */
;;;1549   void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
000000  4901              LDR      r1,|L29.8|
;;;1550   {
;;;1551     /* Check the parameters */
;;;1552     assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
;;;1553   
;;;1554     *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;  
000002  6008              STR      r0,[r1,#0]
;;;1555   }
000004  4770              BX       lr
;;;1556   
                          ENDP

000006  0000              DCW      0x0000
                  |L29.8|
                          DCD      0x4247015c

                          AREA ||i.RCC_ITConfig||, CODE, READONLY, ALIGN=2

                  RCC_ITConfig PROC
;;;2581     */
;;;2582   void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
000000  4a05              LDR      r2,|L30.24|
;;;2583   {
;;;2584     /* Check the parameters */
;;;2585     assert_param(IS_RCC_IT(RCC_IT));
;;;2586     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2587     if (NewState != DISABLE)
000002  2900              CMP      r1,#0
000004  d003              BEQ      |L30.14|
;;;2588     {
;;;2589       /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
;;;2590       *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
000006  7811              LDRB     r1,[r2,#0]
000008  4301              ORRS     r1,r1,r0
00000a  7011              STRB     r1,[r2,#0]
;;;2591     }
;;;2592     else
;;;2593     {
;;;2594       /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
;;;2595       *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
;;;2596     }
;;;2597   }
00000c  4770              BX       lr
                  |L30.14|
00000e  7811              LDRB     r1,[r2,#0]            ;2595
000010  4381              BICS     r1,r1,r0              ;2595
000012  7011              STRB     r1,[r2,#0]            ;2595
000014  4770              BX       lr
;;;2598   
                          ENDP

000016  0000              DCW      0x0000
                  |L30.24|
                          DCD      0x4002380d

                          AREA ||i.RCC_LSEConfig||, CODE, READONLY, ALIGN=2

                  RCC_LSEConfig PROC
;;;378      */
;;;379    void RCC_LSEConfig(uint8_t RCC_LSE)
000000  4906              LDR      r1,|L31.28|
;;;380    {
;;;381      /* Check the parameters */
;;;382      assert_param(IS_RCC_LSE(RCC_LSE));
;;;383    
;;;384      /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
;;;385      /* Reset LSEON bit */
;;;386      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
000002  2200              MOVS     r2,#0
000004  700a              STRB     r2,[r1,#0]
;;;387    
;;;388      /* Reset LSEBYP bit */
;;;389      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
000006  700a              STRB     r2,[r1,#0]
;;;390    
;;;391      /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
;;;392      switch (RCC_LSE)
000008  2801              CMP      r0,#1
00000a  d004              BEQ      |L31.22|
00000c  2804              CMP      r0,#4
00000e  d101              BNE      |L31.20|
;;;393      {
;;;394        case RCC_LSE_ON:
;;;395          /* Set LSEON bit */
;;;396          *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
;;;397          break;
;;;398        case RCC_LSE_Bypass:
;;;399          /* Set LSEBYP and LSEON bits */
;;;400          *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
000010  2005              MOVS     r0,#5
000012  7008              STRB     r0,[r1,#0]
                  |L31.20|
;;;401          break;
;;;402        default:
;;;403          break;
;;;404      }
;;;405    }
000014  4770              BX       lr
                  |L31.22|
000016  2001              MOVS     r0,#1                 ;396
000018  7008              STRB     r0,[r1,#0]            ;396
00001a  4770              BX       lr
;;;406    
                          ENDP

                  |L31.28|
                          DCD      0x40023870

                          AREA ||i.RCC_LSEModeConfig||, CODE, READONLY, ALIGN=2

                  RCC_LSEModeConfig PROC
;;;2383     */
;;;2384   void RCC_LSEModeConfig(uint8_t RCC_Mode)
000000  4906              LDR      r1,|L32.28|
;;;2385   {
;;;2386     /* Check the parameters */
;;;2387     assert_param(IS_RCC_LSE_MODE(RCC_Mode));
;;;2388     
;;;2389     if(RCC_Mode == RCC_LSE_HIGHDRIVE_MODE)
000002  2801              CMP      r0,#1
000004  d004              BEQ      |L32.16|
;;;2390     {
;;;2391       SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
;;;2392     }
;;;2393     else
;;;2394     {
;;;2395       CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
000006  6808              LDR      r0,[r1,#0]
000008  f0200008          BIC      r0,r0,#8
00000c  6008              STR      r0,[r1,#0]
;;;2396     }
;;;2397   }
00000e  4770              BX       lr
                  |L32.16|
000010  6808              LDR      r0,[r1,#0]            ;2391
000012  f0400008          ORR      r0,r0,#8              ;2391
000016  6008              STR      r0,[r1,#0]            ;2391
000018  4770              BX       lr
;;;2398   
                          ENDP

00001a  0000              DCW      0x0000
                  |L32.28|
                          DCD      0x40023870

                          AREA ||i.RCC_LSICmd||, CODE, READONLY, ALIGN=2

                  RCC_LSICmd PROC
;;;418      */
;;;419    void RCC_LSICmd(FunctionalState NewState)
000000  4901              LDR      r1,|L33.8|
;;;420    {
;;;421      /* Check the parameters */
;;;422      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;423    
;;;424      *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
000002  6008              STR      r0,[r1,#0]
;;;425    }
000004  4770              BX       lr
;;;426    
                          ENDP

000006  0000              DCW      0x0000
                  |L33.8|
                          DCD      0x42470e80

                          AREA ||i.RCC_LTDCCLKDivConfig||, CODE, READONLY, ALIGN=2

                  RCC_LTDCCLKDivConfig PROC
;;;1710     */
;;;1711   void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR)
000000  4a03              LDR      r2,|L34.16|
;;;1712   {
;;;1713     uint32_t tmpreg = 0;
;;;1714     
;;;1715     /* Check the parameters */
;;;1716     assert_param(IS_RCC_PLLSAI_DIVR_VALUE(RCC_PLLSAIDivR));
;;;1717     
;;;1718     tmpreg = RCC->DCKCFGR;
000002  6811              LDR      r1,[r2,#0]
;;;1719   
;;;1720     /* Clear PLLSAIDIVR[2:0] bits */
;;;1721     tmpreg &= ~RCC_DCKCFGR_PLLSAIDIVR;
000004  f4213140          BIC      r1,r1,#0x30000
;;;1722   
;;;1723     /* Set PLLSAIDIVR values */
;;;1724     tmpreg |= RCC_PLLSAIDivR;
000008  4301              ORRS     r1,r1,r0
;;;1725   
;;;1726     /* Store the new value */
;;;1727     RCC->DCKCFGR = tmpreg;
00000a  6011              STR      r1,[r2,#0]
;;;1728   }
00000c  4770              BX       lr
;;;1729   
                          ENDP

00000e  0000              DCW      0x0000
                  |L34.16|
                          DCD      0x4002388c

                          AREA ||i.RCC_MCO1Config||, CODE, READONLY, ALIGN=2

                  RCC_MCO1Config PROC
;;;844      */
;;;845    void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
000000  4b03              LDR      r3,|L35.16|
;;;846    {
;;;847      uint32_t tmpreg = 0;
;;;848      
;;;849      /* Check the parameters */
;;;850      assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source));
;;;851      assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));  
;;;852    
;;;853      tmpreg = RCC->CFGR;
000002  681a              LDR      r2,[r3,#0]
;;;854    
;;;855      /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
;;;856      tmpreg &= CFGR_MCO1_RESET_MASK;
000004  f02262ec          BIC      r2,r2,#0x7600000
;;;857    
;;;858      /* Select MCO1 clock source and prescaler */
;;;859      tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
000008  4308              ORRS     r0,r0,r1
00000a  4310              ORRS     r0,r0,r2
;;;860    
;;;861      /* Store the new value */
;;;862      RCC->CFGR = tmpreg;  
00000c  6018              STR      r0,[r3,#0]
;;;863    }
00000e  4770              BX       lr
;;;864    
                          ENDP

                  |L35.16|
                          DCD      0x40023808

                          AREA ||i.RCC_MCO2Config||, CODE, READONLY, ALIGN=2

                  RCC_MCO2Config PROC
;;;882      */
;;;883    void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
000000  4b03              LDR      r3,|L36.16|
;;;884    {
;;;885      uint32_t tmpreg = 0;
;;;886      
;;;887      /* Check the parameters */
;;;888      assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source));
;;;889      assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
;;;890      
;;;891      tmpreg = RCC->CFGR;
000002  681a              LDR      r2,[r3,#0]
;;;892      
;;;893      /* Clear MCO2 and MCO2PRE[2:0] bits */
;;;894      tmpreg &= CFGR_MCO2_RESET_MASK;
000004  f0224278          BIC      r2,r2,#0xf8000000
;;;895    
;;;896      /* Select MCO2 clock source and prescaler */
;;;897      tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
000008  4308              ORRS     r0,r0,r1
00000a  4310              ORRS     r0,r0,r2
;;;898    
;;;899      /* Store the new value */
;;;900      RCC->CFGR = tmpreg;  
00000c  6018              STR      r0,[r3,#0]
;;;901    }
00000e  4770              BX       lr
;;;902    
                          ENDP

                  |L36.16|
                          DCD      0x40023808

                          AREA ||i.RCC_PCLK1Config||, CODE, READONLY, ALIGN=2

                  RCC_PCLK1Config PROC
;;;1164     */
;;;1165   void RCC_PCLK1Config(uint32_t RCC_HCLK)
000000  4a03              LDR      r2,|L37.16|
;;;1166   {
;;;1167     uint32_t tmpreg = 0;
;;;1168   
;;;1169     /* Check the parameters */
;;;1170     assert_param(IS_RCC_PCLK(RCC_HCLK));
;;;1171   
;;;1172     tmpreg = RCC->CFGR;
000002  6811              LDR      r1,[r2,#0]
;;;1173   
;;;1174     /* Clear PPRE1[2:0] bits */
;;;1175     tmpreg &= ~RCC_CFGR_PPRE1;
000004  f42151e0          BIC      r1,r1,#0x1c00
;;;1176   
;;;1177     /* Set PPRE1[2:0] bits according to RCC_HCLK value */
;;;1178     tmpreg |= RCC_HCLK;
000008  4301              ORRS     r1,r1,r0
;;;1179   
;;;1180     /* Store the new value */
;;;1181     RCC->CFGR = tmpreg;
00000a  6011              STR      r1,[r2,#0]
;;;1182   }
00000c  4770              BX       lr
;;;1183   
                          ENDP

00000e  0000              DCW      0x0000
                  |L37.16|
                          DCD      0x40023808

                          AREA ||i.RCC_PCLK2Config||, CODE, READONLY, ALIGN=2

                  RCC_PCLK2Config PROC
;;;1195     */
;;;1196   void RCC_PCLK2Config(uint32_t RCC_HCLK)
000000  4a03              LDR      r2,|L38.16|
;;;1197   {
;;;1198     uint32_t tmpreg = 0;
;;;1199   
;;;1200     /* Check the parameters */
;;;1201     assert_param(IS_RCC_PCLK(RCC_HCLK));
;;;1202   
;;;1203     tmpreg = RCC->CFGR;
000002  6811              LDR      r1,[r2,#0]
;;;1204   
;;;1205     /* Clear PPRE2[2:0] bits */
;;;1206     tmpreg &= ~RCC_CFGR_PPRE2;
000004  f4214160          BIC      r1,r1,#0xe000
;;;1207   
;;;1208     /* Set PPRE2[2:0] bits according to RCC_HCLK value */
;;;1209     tmpreg |= RCC_HCLK << 3;
000008  ea4100c0          ORR      r0,r1,r0,LSL #3
;;;1210   
;;;1211     /* Store the new value */
;;;1212     RCC->CFGR = tmpreg;
00000c  6010              STR      r0,[r2,#0]
;;;1213   }
00000e  4770              BX       lr
;;;1214   
                          ENDP

                  |L38.16|
                          DCD      0x40023808

                          AREA ||i.RCC_PLLCmd||, CODE, READONLY, ALIGN=2

                  RCC_PLLCmd PROC
;;;541      */
;;;542    void RCC_PLLCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L39.8|
;;;543    {
;;;544      /* Check the parameters */
;;;545      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;546      *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
000002  6608              STR      r0,[r1,#0x60]
;;;547    }
000004  4770              BX       lr
;;;548    
                          ENDP

000006  0000              DCW      0x0000
                  |L39.8|
                          DCD      0x42470000

                          AREA ||i.RCC_PLLConfig||, CODE, READONLY, ALIGN=2

                  RCC_PLLConfig PROC
;;;517      */
;;;518    void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
000000  b510              PUSH     {r4,lr}
;;;519    {
000002  9c02              LDR      r4,[sp,#8]
;;;520      /* Check the parameters */
;;;521      assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
;;;522      assert_param(IS_RCC_PLLM_VALUE(PLLM));
;;;523      assert_param(IS_RCC_PLLN_VALUE(PLLN));
;;;524      assert_param(IS_RCC_PLLP_VALUE(PLLP));
;;;525      assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
;;;526    
;;;527      RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
000004  ea411182          ORR      r1,r1,r2,LSL #6
000008  f04f32ff          MOV      r2,#0xffffffff
00000c  eb020253          ADD      r2,r2,r3,LSR #1
000010  ea414102          ORR      r1,r1,r2,LSL #16
000014  4301              ORRS     r1,r1,r0
000016  ea416004          ORR      r0,r1,r4,LSL #24
00001a  4901              LDR      r1,|L40.32|
00001c  6008              STR      r0,[r1,#0]
;;;528                     (PLLQ << 24);
;;;529    }
00001e  bd10              POP      {r4,pc}
;;;530    #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
                          ENDP

                  |L40.32|
                          DCD      0x40023804

                          AREA ||i.RCC_PLLI2SCmd||, CODE, READONLY, ALIGN=2

                  RCC_PLLI2SCmd PROC
;;;710      */
;;;711    void RCC_PLLI2SCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L41.8|
;;;712    {
;;;713      /* Check the parameters */
;;;714      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;715      *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
000002  6688              STR      r0,[r1,#0x68]
;;;716    }
000004  4770              BX       lr
;;;717    
                          ENDP

000006  0000              DCW      0x0000
                  |L41.8|
                          DCD      0x42470000

                          AREA ||i.RCC_PLLI2SConfig||, CODE, READONLY, ALIGN=2

                  RCC_PLLI2SConfig PROC
;;;571      */
;;;572    void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
000000  0180              LSLS     r0,r0,#6
;;;573    {
;;;574      /* Check the parameters */
;;;575      assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
;;;576      assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
;;;577    
;;;578      RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
000002  ea407001          ORR      r0,r0,r1,LSL #28
000006  4901              LDR      r1,|L42.12|
000008  6008              STR      r0,[r1,#0]
;;;579    }
00000a  4770              BX       lr
;;;580    #endif /* STM32F40_41xxx || STM32F401xx */
                          ENDP

                  |L42.12|
                          DCD      0x40023884

                          AREA ||i.RCC_PLLSAICmd||, CODE, READONLY, ALIGN=2

                  RCC_PLLSAICmd PROC
;;;801      */
;;;802    void RCC_PLLSAICmd(FunctionalState NewState)
000000  4901              LDR      r1,|L43.8|
;;;803    {
;;;804      /* Check the parameters */
;;;805      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;806      *(__IO uint32_t *) CR_PLLSAION_BB = (uint32_t)NewState;
000002  6708              STR      r0,[r1,#0x70]
;;;807    }
000004  4770              BX       lr
;;;808    
                          ENDP

000006  0000              DCW      0x0000
                  |L43.8|
                          DCD      0x42470000

                          AREA ||i.RCC_PLLSAIConfig||, CODE, READONLY, ALIGN=2

                  RCC_PLLSAIConfig PROC
;;;781      */
;;;782    void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)
000000  0180              LSLS     r0,r0,#6
;;;783    {
;;;784      /* Check the parameters */
;;;785      assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN));
;;;786      assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR));
;;;787      assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIQ));
;;;788      
;;;789      RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIQ << 24) | (PLLSAIR << 28);
000002  ea406001          ORR      r0,r0,r1,LSL #24
000006  4902              LDR      r1,|L44.16|
000008  ea407002          ORR      r0,r0,r2,LSL #28
00000c  6008              STR      r0,[r1,#0]
;;;790    }
00000e  4770              BX       lr
;;;791    #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
                          ENDP

                  |L44.16|
                          DCD      0x40023888

                          AREA ||i.RCC_RTCCLKCmd||, CODE, READONLY, ALIGN=2

                  RCC_RTCCLKCmd PROC
;;;1432     */
;;;1433   void RCC_RTCCLKCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L45.8|
;;;1434   {
;;;1435     /* Check the parameters */
;;;1436     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1437   
;;;1438     *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
000002  6008              STR      r0,[r1,#0]
;;;1439   }
000004  4770              BX       lr
;;;1440   
                          ENDP

000006  0000              DCW      0x0000
                  |L45.8|
                          DCD      0x42470e3c

                          AREA ||i.RCC_RTCCLKConfig||, CODE, READONLY, ALIGN=2

                  RCC_RTCCLKConfig PROC
;;;1400     */
;;;1401   void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
000000  f3c02101          UBFX     r1,r0,#8,#2
;;;1402   {
;;;1403     uint32_t tmpreg = 0;
;;;1404   
;;;1405     /* Check the parameters */
;;;1406     assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
;;;1407   
;;;1408     if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
000004  2903              CMP      r1,#3
000006  d107              BNE      |L46.24|
;;;1409     { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
;;;1410       tmpreg = RCC->CFGR;
000008  4b07              LDR      r3,|L46.40|
00000a  6819              LDR      r1,[r3,#0]
;;;1411   
;;;1412       /* Clear RTCPRE[4:0] bits */
;;;1413       tmpreg &= ~RCC_CFGR_RTCPRE;
00000c  f42112f8          BIC      r2,r1,#0x1f0000
;;;1414   
;;;1415       /* Configure HSE division factor for RTC clock */
;;;1416       tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
000010  4906              LDR      r1,|L46.44|
000012  4001              ANDS     r1,r1,r0
000014  4311              ORRS     r1,r1,r2
;;;1417   
;;;1418       /* Store the new value */
;;;1419       RCC->CFGR = tmpreg;
000016  6019              STR      r1,[r3,#0]
                  |L46.24|
;;;1420     }
;;;1421       
;;;1422     /* Select the RTC clock source */
;;;1423     RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
000018  4a03              LDR      r2,|L46.40|
00001a  3268              ADDS     r2,r2,#0x68
00001c  6811              LDR      r1,[r2,#0]
00001e  f3c0000b          UBFX     r0,r0,#0,#12
000022  4301              ORRS     r1,r1,r0
000024  6011              STR      r1,[r2,#0]
;;;1424   }
000026  4770              BX       lr
;;;1425   
                          ENDP

                  |L46.40|
                          DCD      0x40023808
                  |L46.44|
                          DCD      0x0ffffcff

                          AREA ||i.RCC_SAIBlockACLKConfig||, CODE, READONLY, ALIGN=2

                  RCC_SAIBlockACLKConfig PROC
;;;1573     */
;;;1574   void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource)
000000  4a03              LDR      r2,|L47.16|
;;;1575   {
;;;1576     uint32_t tmpreg = 0;
;;;1577     
;;;1578     /* Check the parameters */
;;;1579     assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource));
;;;1580     
;;;1581     tmpreg = RCC->DCKCFGR;
000002  6811              LDR      r1,[r2,#0]
;;;1582   
;;;1583     /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */
;;;1584     tmpreg &= ~RCC_DCKCFGR_SAI1ASRC;
000004  f4211140          BIC      r1,r1,#0x300000
;;;1585   
;;;1586     /* Set SAI Block A source selection value */
;;;1587     tmpreg |= RCC_SAIBlockACLKSource;
000008  4301              ORRS     r1,r1,r0
;;;1588   
;;;1589     /* Store the new value */
;;;1590     RCC->DCKCFGR = tmpreg;
00000a  6011              STR      r1,[r2,#0]
;;;1591   }
00000c  4770              BX       lr
;;;1592   
                          ENDP

00000e  0000              DCW      0x0000
                  |L47.16|
                          DCD      0x4002388c

                          AREA ||i.RCC_SAIBlockBCLKConfig||, CODE, READONLY, ALIGN=2

                  RCC_SAIBlockBCLKConfig PROC
;;;1609     */
;;;1610   void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource)
000000  4a03              LDR      r2,|L48.16|
;;;1611   {
;;;1612     uint32_t tmpreg = 0;
;;;1613     
;;;1614     /* Check the parameters */
;;;1615     assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource));
;;;1616     
;;;1617     tmpreg = RCC->DCKCFGR;
000002  6811              LDR      r1,[r2,#0]
;;;1618   
;;;1619     /* Clear RCC_DCKCFGR_SAI1BSRC[1:0] bits */
;;;1620     tmpreg &= ~RCC_DCKCFGR_SAI1BSRC;
000004  f4210140          BIC      r1,r1,#0xc00000
;;;1621   
;;;1622     /* Set SAI Block B source selection value */
;;;1623     tmpreg |= RCC_SAIBlockBCLKSource;
000008  4301              ORRS     r1,r1,r0
;;;1624   
;;;1625     /* Store the new value */
;;;1626     RCC->DCKCFGR = tmpreg;
00000a  6011              STR      r1,[r2,#0]
;;;1627   }
00000c  4770              BX       lr
;;;1628   #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
                          ENDP

00000e  0000              DCW      0x0000
                  |L48.16|
                          DCD      0x4002388c

                          AREA ||i.RCC_SAIPLLI2SClkDivConfig||, CODE, READONLY, ALIGN=2

                  RCC_SAIPLLI2SClkDivConfig PROC
;;;1642     */
;;;1643   void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ)  
000000  4a03              LDR      r2,|L49.16|
;;;1644   {
;;;1645     uint32_t tmpreg = 0;
;;;1646     
;;;1647     /* Check the parameters */
;;;1648     assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(RCC_PLLI2SDivQ));
;;;1649     
;;;1650     tmpreg = RCC->DCKCFGR;
000002  6811              LDR      r1,[r2,#0]
;;;1651   
;;;1652     /* Clear PLLI2SDIVQ[4:0] bits */
;;;1653     tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVQ);
000004  f021011f          BIC      r1,r1,#0x1f
;;;1654   
;;;1655     /* Set PLLI2SDIVQ values */
;;;1656     tmpreg |= (RCC_PLLI2SDivQ - 1);
000008  1e40              SUBS     r0,r0,#1
00000a  4301              ORRS     r1,r1,r0
;;;1657   
;;;1658     /* Store the new value */
;;;1659     RCC->DCKCFGR = tmpreg;
00000c  6011              STR      r1,[r2,#0]
;;;1660   }
00000e  4770              BX       lr
;;;1661   
                          ENDP

                  |L49.16|
                          DCD      0x4002388c

                          AREA ||i.RCC_SAIPLLSAIClkDivConfig||, CODE, READONLY, ALIGN=2

                  RCC_SAIPLLSAIClkDivConfig PROC
;;;1674     */
;;;1675   void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ)  
000000  4a04              LDR      r2,|L50.20|
;;;1676   {
;;;1677     uint32_t tmpreg = 0;
;;;1678     
;;;1679     /* Check the parameters */
;;;1680     assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(RCC_PLLSAIDivQ));
;;;1681     
;;;1682     tmpreg = RCC->DCKCFGR;
000002  6811              LDR      r1,[r2,#0]
;;;1683   
;;;1684     /* Clear PLLI2SDIVQ[4:0] and PLLSAIDIVQ[4:0] bits */
;;;1685     tmpreg &= ~(RCC_DCKCFGR_PLLSAIDIVQ);
000004  f42151f8          BIC      r1,r1,#0x1f00
;;;1686   
;;;1687     /* Set PLLSAIDIVQ values */
;;;1688     tmpreg |= ((RCC_PLLSAIDivQ - 1) << 8);
000008  1e40              SUBS     r0,r0,#1
00000a  ea412000          ORR      r0,r1,r0,LSL #8
;;;1689   
;;;1690     /* Store the new value */
;;;1691     RCC->DCKCFGR = tmpreg;
00000e  6010              STR      r0,[r2,#0]
;;;1692   }
000010  4770              BX       lr
;;;1693   
                          ENDP

000012  0000              DCW      0x0000
                  |L50.20|
                          DCD      0x4002388c

                          AREA ||i.RCC_SYSCLKConfig||, CODE, READONLY, ALIGN=2

                  RCC_SYSCLKConfig PROC
;;;1078     */
;;;1079   void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
000000  4a03              LDR      r2,|L51.16|
;;;1080   {
;;;1081     uint32_t tmpreg = 0;
;;;1082   
;;;1083     /* Check the parameters */
;;;1084     assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
;;;1085   
;;;1086     tmpreg = RCC->CFGR;
000002  6811              LDR      r1,[r2,#0]
;;;1087   
;;;1088     /* Clear SW[1:0] bits */
;;;1089     tmpreg &= ~RCC_CFGR_SW;
000004  f0210103          BIC      r1,r1,#3
;;;1090   
;;;1091     /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
;;;1092     tmpreg |= RCC_SYSCLKSource;
000008  4301              ORRS     r1,r1,r0
;;;1093   
;;;1094     /* Store the new value */
;;;1095     RCC->CFGR = tmpreg;
00000a  6011              STR      r1,[r2,#0]
;;;1096   }
00000c  4770              BX       lr
;;;1097   
                          ENDP

00000e  0000              DCW      0x0000
                  |L51.16|
                          DCD      0x40023808

                          AREA ||i.RCC_TIMCLKPresConfig||, CODE, READONLY, ALIGN=2

                  RCC_TIMCLKPresConfig PROC
;;;1747     */
;;;1748   void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
000000  4901              LDR      r1,|L52.8|
;;;1749   {
;;;1750     /* Check the parameters */
;;;1751     assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler));
;;;1752   
;;;1753     *(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler;
000002  6008              STR      r0,[r1,#0]
;;;1754   }
000004  4770              BX       lr
;;;1755   
                          ENDP

000006  0000              DCW      0x0000
                  |L52.8|
                          DCD      0x424711e0

                          AREA ||i.RCC_WaitForHSEStartUp||, CODE, READONLY, ALIGN=1

                  RCC_WaitForHSEStartUp PROC
;;;286      */
;;;287    ErrorStatus RCC_WaitForHSEStartUp(void)
000000  b518              PUSH     {r3,r4,lr}
;;;288    {
;;;289      __IO uint32_t startupcounter = 0;
000002  2000              MOVS     r0,#0
000004  9000              STR      r0,[sp,#0]
;;;290      ErrorStatus status = ERROR;
;;;291      FlagStatus hsestatus = RESET;
;;;292      /* Wait till HSE is ready and if Time out is reached exit */
;;;293      do
;;;294      {
;;;295        hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
;;;296        startupcounter++;
;;;297      } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
000006  f44f44a0          MOV      r4,#0x5000
                  |L53.10|
00000a  2031              MOVS     r0,#0x31              ;295
00000c  f7fffffe          BL       RCC_GetFlagStatus
000010  9900              LDR      r1,[sp,#0]            ;296
000012  1c49              ADDS     r1,r1,#1              ;296
000014  9100              STR      r1,[sp,#0]            ;296
000016  9900              LDR      r1,[sp,#0]
000018  42a1              CMP      r1,r4
00001a  d001              BEQ      |L53.32|
00001c  2800              CMP      r0,#0
00001e  d0f4              BEQ      |L53.10|
                  |L53.32|
;;;298    
;;;299      if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
000020  2031              MOVS     r0,#0x31
000022  f7fffffe          BL       RCC_GetFlagStatus
000026  b108              CBZ      r0,|L53.44|
;;;300      {
;;;301        status = SUCCESS;
000028  2001              MOVS     r0,#1
;;;302      }
;;;303      else
;;;304      {
;;;305        status = ERROR;
;;;306      }
;;;307      return (status);
;;;308    }
00002a  bd18              POP      {r3,r4,pc}
                  |L53.44|
00002c  2000              MOVS     r0,#0                 ;305
00002e  bd18              POP      {r3,r4,pc}
;;;309    
                          ENDP


                          AREA ||.data||, DATA, ALIGN=0

                  APBAHBPrescTable
000000  00000000          DCB      0x00,0x00,0x00,0x00
000004  01020304          DCB      0x01,0x02,0x03,0x04
000008  01020304          DCB      0x01,0x02,0x03,0x04
00000c  06070809          DCB      0x06,0x07,0x08,0x09

;*** Start embedded assembler ***

#line 1 "..\\..\\Libraries\\STM32F4xx_StdPeriph_Driver\\src\\stm32f4xx_rcc.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f4xx_rcc_c_49e27980____REV16|
#line 129 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h"
|__asm___15_stm32f4xx_rcc_c_49e27980____REV16| PROC
#line 130

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f4xx_rcc_c_49e27980____REVSH|
#line 144
|__asm___15_stm32f4xx_rcc_c_49e27980____REVSH| PROC
#line 145

 revsh r0, r0
 bx lr
	ENDP
	AREA ||.rrx_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f4xx_rcc_c_49e27980____RRX|
#line 300
|__asm___15_stm32f4xx_rcc_c_49e27980____RRX| PROC
#line 301

 rrx r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***