AGV / agv_shengyiPPxiaoche · Files

; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\flash\obj\stm32f4xx_pwr.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\stm32f4xx_pwr.d --cpu=Cortex-M4.fp --apcs=interwork -O1 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Include -I..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\uCOS-III\uC-CPU -I..\..\uCOS-III\uC-LIB -I..\..\uCOS-III\uCOS-III\Ports -I..\..\uCOS-III\uCOS-III\Source -I..\..\uCOS-III\uC-CPU\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uC-LIB\Ports\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uCOS-III\Ports\ARM-Cortex-M4\Generic\RealView -I..\..\User -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\libapp -I..\..\RL-ARM\Config -I..\..\RL-ARM\Driver -I..\..\RL-ARM\RL-RTX\inc -I..\..\User\bsp\BSP -I..\..\RL-ARM\RL-CAN -I..\..\Libraries\DSP_LIB\Include -I..\..\MODBUS\modbus\rtu -I..\..\MODBUS\BARE\port -I..\..\MODBUS\modbus\include -I..\..\User\bsp\BSP -I..\..\PLC -I..\..\Avoid -I..\..\User\parameter -I..\..\User\LaserMotionCtr -I..\..\User\W5100S -I..\..\User\bsp -I..\..\User\CHASSIS -I..\..\User\CONTROLFUNCTION -I..\..\User\DATAUPDATE -I..\..\User\HARAWARE -I..\..\User\MOTORDRIVER -I..\..\User\NAVAGATION -I..\..\User\PLATFORM -I..\..\User\SENSOR -I.\RTE\_Flash -IC:\Users\YDJ\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include -IC:\Users\YDJ\AppData\Local\Arm\Packs\Keil\STM32F4xx_DFP\2.13.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include -D__UVISION_VERSION=527 -D_RTE_ -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -D__RTX -D__FPU_USED=1 --omf_browse=.\flash\obj\stm32f4xx_pwr.crf ..\..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_pwr.c]
                          THUMB

                          AREA ||i.PWR_BackupAccessCmd||, CODE, READONLY, ALIGN=2

                  PWR_BackupAccessCmd PROC
;;;178      */
;;;179    void PWR_BackupAccessCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L1.8|
;;;180    {
;;;181      /* Check the parameters */
;;;182      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;183      
;;;184      *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
000002  6208              STR      r0,[r1,#0x20]
;;;185    }
000004  4770              BX       lr
;;;186    
                          ENDP

000006  0000              DCW      0x0000
                  |L1.8|
                          DCD      0x420e0000

                          AREA ||i.PWR_BackupRegulatorCmd||, CODE, READONLY, ALIGN=2

                  PWR_BackupRegulatorCmd PROC
;;;410      */
;;;411    void PWR_BackupRegulatorCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L2.8|
;;;412    {
;;;413      /* Check the parameters */
;;;414      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;415    
;;;416      *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
000002  6008              STR      r0,[r1,#0]
;;;417    }
000004  4770              BX       lr
;;;418    
                          ENDP

000006  0000              DCW      0x0000
                  |L2.8|
                          DCD      0x420e00a4

                          AREA ||i.PWR_ClearFlag||, CODE, READONLY, ALIGN=2

                  PWR_ClearFlag PROC
;;;1003     */
;;;1004   void PWR_ClearFlag(uint32_t PWR_FLAG)
000000  4902              LDR      r1,|L3.12|
;;;1005   {
;;;1006     /* Check the parameters */
;;;1007     assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
;;;1008     
;;;1009   #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
;;;1010     if (PWR_FLAG != PWR_FLAG_UDRDY)
;;;1011     {
;;;1012       PWR->CR |=  PWR_FLAG << 2;
;;;1013     }
;;;1014     else
;;;1015     {
;;;1016       PWR->CSR |= PWR_FLAG_UDRDY;
;;;1017     }
;;;1018   #endif /* STM32F427_437xx ||  STM32F429_439xx */
;;;1019   
;;;1020   #if defined (STM32F40_41xxx) || defined (STM32F401xx) || defined (STM32F411xE) 
;;;1021     PWR->CR |=  PWR_FLAG << 2;
000002  680a              LDR      r2,[r1,#0]
000004  ea420080          ORR      r0,r2,r0,LSL #2
000008  6008              STR      r0,[r1,#0]
;;;1022   #endif /* STM32F40_41xxx  || STM32F401xx || STM32F411xE */
;;;1023   }
00000a  4770              BX       lr
;;;1024   
                          ENDP

                  |L3.12|
                          DCD      0x40007000

                          AREA ||i.PWR_DeInit||, CODE, READONLY, ALIGN=1

                  PWR_DeInit PROC
;;;163      */
;;;164    void PWR_DeInit(void)
000000  b510              PUSH     {r4,lr}
;;;165    {
;;;166      RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
000002  2101              MOVS     r1,#1
000004  070c              LSLS     r4,r1,#28
000006  4620              MOV      r0,r4
000008  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;167      RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
00000c  4620              MOV      r0,r4
00000e  e8bd4010          POP      {r4,lr}
000012  2100              MOVS     r1,#0
000014  f7ffbffe          B.W      RCC_APB1PeriphResetCmd
;;;168    }
;;;169    
                          ENDP


                          AREA ||i.PWR_EnterSTANDBYMode||, CODE, READONLY, ALIGN=2

                  PWR_EnterSTANDBYMode PROC
;;;915      */
;;;916    void PWR_EnterSTANDBYMode(void)
000000  4805              LDR      r0,|L5.24|
;;;917    {
;;;918      /* Select STANDBY mode */
;;;919      PWR->CR |= PWR_CR_PDDS;
000002  6801              LDR      r1,[r0,#0]
000004  f0410102          ORR      r1,r1,#2
000008  6001              STR      r1,[r0,#0]
;;;920      
;;;921      /* Set SLEEPDEEP bit of Cortex System Control Register */
;;;922      SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
00000a  4804              LDR      r0,|L5.28|
00000c  6801              LDR      r1,[r0,#0]
00000e  f0410104          ORR      r1,r1,#4
000012  6001              STR      r1,[r0,#0]
;;;923      
;;;924      /* This option is used to ensure that store operations are completed */
;;;925    #if defined ( __CC_ARM   )
;;;926      __force_stores();
;;;927    #endif
;;;928      /* Request Wait For Interrupt */
;;;929      __WFI();
000014  bf30              WFI      
;;;930    }
000016  4770              BX       lr
;;;931    
                          ENDP

                  |L5.24|
                          DCD      0x40007000
                  |L5.28|
                          DCD      0xe000ed10

                          AREA ||i.PWR_EnterSTOPMode||, CODE, READONLY, ALIGN=2

                  PWR_EnterSTOPMode PROC
;;;802      */
;;;803    void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
000000  b510              PUSH     {r4,lr}
;;;804    {
;;;805      uint32_t tmpreg = 0;
;;;806      
;;;807      /* Check the parameters */
;;;808      assert_param(IS_PWR_REGULATOR(PWR_Regulator));
;;;809      assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
;;;810      
;;;811      /* Select the regulator state in STOP mode ---------------------------------*/
;;;812      tmpreg = PWR->CR;
000002  4b0b              LDR      r3,|L6.48|
000004  681a              LDR      r2,[r3,#0]
;;;813      /* Clear PDDS and LPDS bits */
;;;814      tmpreg &= CR_DS_MASK;
000006  f6404403          MOV      r4,#0xc03
00000a  43a2              BICS     r2,r2,r4
;;;815      
;;;816      /* Set LPDS, MRLVDS and LPLVDS bits according to PWR_Regulator value */
;;;817      tmpreg |= PWR_Regulator;
00000c  4302              ORRS     r2,r2,r0
;;;818      
;;;819      /* Store the new value */
;;;820      PWR->CR = tmpreg;
00000e  601a              STR      r2,[r3,#0]
;;;821      
;;;822      /* Set SLEEPDEEP bit of Cortex System Control Register */
;;;823      SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
000010  4808              LDR      r0,|L6.52|
000012  6802              LDR      r2,[r0,#0]
000014  f0420204          ORR      r2,r2,#4
000018  6002              STR      r2,[r0,#0]
;;;824      
;;;825      /* Select STOP mode entry --------------------------------------------------*/
;;;826      if(PWR_STOPEntry == PWR_STOPEntry_WFI)
00001a  2901              CMP      r1,#1
00001c  d005              BEQ      |L6.42|
;;;827      {   
;;;828        /* Request Wait For Interrupt */
;;;829        __WFI();
;;;830      }
;;;831      else
;;;832      {
;;;833        /* Request Wait For Event */
;;;834        __WFE();
00001e  bf20              WFE      
                  |L6.32|
;;;835      }
;;;836      /* Reset SLEEPDEEP bit of Cortex System Control Register */
;;;837      SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);  
000020  6801              LDR      r1,[r0,#0]
000022  f0210104          BIC      r1,r1,#4
000026  6001              STR      r1,[r0,#0]
;;;838    }
000028  bd10              POP      {r4,pc}
                  |L6.42|
00002a  bf30              WFI                            ;829
00002c  e7f8              B        |L6.32|
;;;839    
                          ENDP

00002e  0000              DCW      0x0000
                  |L6.48|
                          DCD      0x40007000
                  |L6.52|
                          DCD      0xe000ed10

                          AREA ||i.PWR_EnterUnderDriveSTOPMode||, CODE, READONLY, ALIGN=2

                  PWR_EnterUnderDriveSTOPMode PROC
;;;866      */
;;;867    void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
000000  b510              PUSH     {r4,lr}
;;;868    {
;;;869      uint32_t tmpreg = 0;
;;;870      
;;;871      /* Check the parameters */
;;;872      assert_param(IS_PWR_REGULATOR_UNDERDRIVE(PWR_Regulator));
;;;873      assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
;;;874      
;;;875      /* Select the regulator state in STOP mode ---------------------------------*/
;;;876      tmpreg = PWR->CR;
000002  4b0b              LDR      r3,|L7.48|
000004  681a              LDR      r2,[r3,#0]
;;;877      /* Clear PDDS and LPDS bits */
;;;878      tmpreg &= CR_DS_MASK;
000006  f6404403          MOV      r4,#0xc03
00000a  43a2              BICS     r2,r2,r4
;;;879      
;;;880      /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
;;;881      tmpreg |= PWR_Regulator;
00000c  4302              ORRS     r2,r2,r0
;;;882      
;;;883      /* Store the new value */
;;;884      PWR->CR = tmpreg;
00000e  601a              STR      r2,[r3,#0]
;;;885      
;;;886      /* Set SLEEPDEEP bit of Cortex System Control Register */
;;;887      SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
000010  4808              LDR      r0,|L7.52|
000012  6802              LDR      r2,[r0,#0]
000014  f0420204          ORR      r2,r2,#4
000018  6002              STR      r2,[r0,#0]
;;;888      
;;;889      /* Select STOP mode entry --------------------------------------------------*/
;;;890      if(PWR_STOPEntry == PWR_STOPEntry_WFI)
00001a  2901              CMP      r1,#1
00001c  d005              BEQ      |L7.42|
;;;891      {   
;;;892        /* Request Wait For Interrupt */
;;;893        __WFI();
;;;894      }
;;;895      else
;;;896      {
;;;897        /* Request Wait For Event */
;;;898        __WFE();
00001e  bf20              WFE      
                  |L7.32|
;;;899      }
;;;900      /* Reset SLEEPDEEP bit of Cortex System Control Register */
;;;901      SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);  
000020  6801              LDR      r1,[r0,#0]
000022  f0210104          BIC      r1,r1,#4
000026  6001              STR      r1,[r0,#0]
;;;902    }
000028  bd10              POP      {r4,pc}
                  |L7.42|
00002a  bf30              WFI                            ;893
00002c  e7f8              B        |L7.32|
;;;903    
                          ENDP

00002e  0000              DCW      0x0000
                  |L7.48|
                          DCD      0x40007000
                  |L7.52|
                          DCD      0xe000ed10

                          AREA ||i.PWR_FlashPowerDownCmd||, CODE, READONLY, ALIGN=2

                  PWR_FlashPowerDownCmd PROC
;;;656      */
;;;657    void PWR_FlashPowerDownCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L8.8|
;;;658    {
;;;659      /* Check the parameters */
;;;660      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;661    
;;;662      *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState;
000002  6248              STR      r0,[r1,#0x24]
;;;663    }
000004  4770              BX       lr
;;;664    
                          ENDP

000006  0000              DCW      0x0000
                  |L8.8|
                          DCD      0x420e0000

                          AREA ||i.PWR_GetFlagStatus||, CODE, READONLY, ALIGN=2

                  PWR_GetFlagStatus PROC
;;;975      */
;;;976    FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
000000  4601              MOV      r1,r0
;;;977    {
;;;978      FlagStatus bitstatus = RESET;
000002  2000              MOVS     r0,#0
;;;979      
;;;980      /* Check the parameters */
;;;981      assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
;;;982      
;;;983      if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
000004  4a02              LDR      r2,|L9.16|
000006  6852              LDR      r2,[r2,#4]
000008  420a              TST      r2,r1
00000a  d000              BEQ      |L9.14|
;;;984      {
;;;985        bitstatus = SET;
00000c  2001              MOVS     r0,#1
                  |L9.14|
;;;986      }
;;;987      else
;;;988      {
;;;989        bitstatus = RESET;
;;;990      }
;;;991      /* Return the flag status */
;;;992      return bitstatus;
;;;993    }
00000e  4770              BX       lr
;;;994    
                          ENDP

                  |L9.16|
                          DCD      0x40007000

                          AREA ||i.PWR_MainRegulatorModeConfig||, CODE, READONLY, ALIGN=2

                  PWR_MainRegulatorModeConfig PROC
;;;432      */
;;;433    void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
000000  4a03              LDR      r2,|L10.16|
;;;434    {
;;;435      uint32_t tmpreg = 0;
;;;436    	
;;;437      /* Check the parameters */
;;;438      assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage));
;;;439    
;;;440      tmpreg = PWR->CR;
000002  6811              LDR      r1,[r2,#0]
;;;441      
;;;442      /* Clear VOS[15:14] bits */
;;;443      tmpreg &= CR_VOS_MASK;
000004  f4214140          BIC      r1,r1,#0xc000
;;;444      
;;;445      /* Set VOS[15:14] bits according to PWR_Regulator_Voltage value */
;;;446      tmpreg |= PWR_Regulator_Voltage;
000008  4301              ORRS     r1,r1,r0
;;;447      
;;;448      /* Store the new value */
;;;449      PWR->CR = tmpreg;
00000a  6011              STR      r1,[r2,#0]
;;;450    }
00000c  4770              BX       lr
;;;451    
                          ENDP

00000e  0000              DCW      0x0000
                  |L10.16|
                          DCD      0x40007000

                          AREA ||i.PWR_OverDriveCmd||, CODE, READONLY, ALIGN=2

                  PWR_OverDriveCmd PROC
;;;467      */
;;;468    void PWR_OverDriveCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L11.8|
;;;469    {
;;;470      /* Check the parameters */
;;;471      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;472      
;;;473      /* Set/Reset the ODEN bit to enable/disable the Over Drive mode */
;;;474      *(__IO uint32_t *) CR_ODEN_BB = (uint32_t)NewState;
000002  6408              STR      r0,[r1,#0x40]
;;;475    }
000004  4770              BX       lr
;;;476    
                          ENDP

000006  0000              DCW      0x0000
                  |L11.8|
                          DCD      0x420e0000

                          AREA ||i.PWR_OverDriveSWCmd||, CODE, READONLY, ALIGN=2

                  PWR_OverDriveSWCmd PROC
;;;485      */
;;;486    void PWR_OverDriveSWCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L12.8|
;;;487    {
;;;488      /* Check the parameters */
;;;489      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;490    
;;;491      /* Set/Reset the ODSWEN bit to enable/disable the Over Drive switching mode */
;;;492      *(__IO uint32_t *) CR_ODSWEN_BB = (uint32_t)NewState;
000002  6448              STR      r0,[r1,#0x44]
;;;493    }
000004  4770              BX       lr
;;;494    
                          ENDP

000006  0000              DCW      0x0000
                  |L12.8|
                          DCD      0x420e0000

                          AREA ||i.PWR_PVDCmd||, CODE, READONLY, ALIGN=2

                  PWR_PVDCmd PROC
;;;251      */
;;;252    void PWR_PVDCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L13.8|
;;;253    {
;;;254      /* Check the parameters */
;;;255      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;256      
;;;257      *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
000002  6108              STR      r0,[r1,#0x10]
;;;258    }
000004  4770              BX       lr
;;;259    
                          ENDP

000006  0000              DCW      0x0000
                  |L13.8|
                          DCD      0x420e0000

                          AREA ||i.PWR_PVDLevelConfig||, CODE, READONLY, ALIGN=2

                  PWR_PVDLevelConfig PROC
;;;226      */
;;;227    void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
000000  4a03              LDR      r2,|L14.16|
;;;228    {
;;;229      uint32_t tmpreg = 0;
;;;230      
;;;231      /* Check the parameters */
;;;232      assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
;;;233      
;;;234      tmpreg = PWR->CR;
000002  6811              LDR      r1,[r2,#0]
;;;235      
;;;236      /* Clear PLS[7:5] bits */
;;;237      tmpreg &= CR_PLS_MASK;
000004  f02101e0          BIC      r1,r1,#0xe0
;;;238      
;;;239      /* Set PLS[7:5] bits according to PWR_PVDLevel value */
;;;240      tmpreg |= PWR_PVDLevel;
000008  4301              ORRS     r1,r1,r0
;;;241      
;;;242      /* Store the new value */
;;;243      PWR->CR = tmpreg;
00000a  6011              STR      r1,[r2,#0]
;;;244    }
00000c  4770              BX       lr
;;;245    
                          ENDP

00000e  0000              DCW      0x0000
                  |L14.16|
                          DCD      0x40007000

                          AREA ||i.PWR_UnderDriveCmd||, CODE, READONLY, ALIGN=2

                  PWR_UnderDriveCmd PROC
;;;512      */
;;;513    void PWR_UnderDriveCmd(FunctionalState NewState)
000000  4906              LDR      r1,|L15.28|
;;;514    {
;;;515      /* Check the parameters */
;;;516      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;517    
;;;518      if (NewState != DISABLE)
000002  2800              CMP      r0,#0
000004  d004              BEQ      |L15.16|
;;;519      {
;;;520        /* Set the UDEN[1:0] bits to enable the Under Drive mode */
;;;521        PWR->CR |= (uint32_t)PWR_CR_UDEN;
000006  6808              LDR      r0,[r1,#0]
000008  f4402040          ORR      r0,r0,#0xc0000
00000c  6008              STR      r0,[r1,#0]
;;;522      }
;;;523      else
;;;524      {
;;;525        /* Reset the UDEN[1:0] bits to disable the Under Drive mode */
;;;526        PWR->CR &= (uint32_t)(~PWR_CR_UDEN);
;;;527      }
;;;528    }
00000e  4770              BX       lr
                  |L15.16|
000010  6808              LDR      r0,[r1,#0]            ;526
000012  f4202040          BIC      r0,r0,#0xc0000        ;526
000016  6008              STR      r0,[r1,#0]            ;526
000018  4770              BX       lr
;;;529    
                          ENDP

00001a  0000              DCW      0x0000
                  |L15.28|
                          DCD      0x40007000

                          AREA ||i.PWR_WakeUpPinCmd||, CODE, READONLY, ALIGN=2

                  PWR_WakeUpPinCmd PROC
;;;285      */
;;;286    void PWR_WakeUpPinCmd(FunctionalState NewState)
000000  4901              LDR      r1,|L16.8|
;;;287    {
;;;288      /* Check the parameters */  
;;;289      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;290    
;;;291      *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
000002  6008              STR      r0,[r1,#0]
;;;292    }
000004  4770              BX       lr
;;;293    #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
                          ENDP

000006  0000              DCW      0x0000
                  |L16.8|
                          DCD      0x420e00a0

;*** Start embedded assembler ***

#line 1 "..\\..\\Libraries\\STM32F4xx_StdPeriph_Driver\\src\\stm32f4xx_pwr.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f4xx_pwr_c_0c2a8b75____REV16|
#line 129 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h"
|__asm___15_stm32f4xx_pwr_c_0c2a8b75____REV16| PROC
#line 130

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f4xx_pwr_c_0c2a8b75____REVSH|
#line 144
|__asm___15_stm32f4xx_pwr_c_0c2a8b75____REVSH| PROC
#line 145

 revsh r0, r0
 bx lr
	ENDP
	AREA ||.rrx_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f4xx_pwr_c_0c2a8b75____RRX|
#line 300
|__asm___15_stm32f4xx_pwr_c_0c2a8b75____RRX| PROC
#line 301

 rrx r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***