AGV / agv_shengyiPPxiaoche · Files

; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\flash\obj\lib_mem.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\lib_mem.d --cpu=Cortex-M4.fp --apcs=interwork -O1 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Include -I..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\uCOS-III\uC-CPU -I..\..\uCOS-III\uC-LIB -I..\..\uCOS-III\uCOS-III\Ports -I..\..\uCOS-III\uCOS-III\Source -I..\..\uCOS-III\uC-CPU\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uC-LIB\Ports\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uCOS-III\Ports\ARM-Cortex-M4\Generic\RealView -I..\..\User -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\libapp -I..\..\RL-ARM\Config -I..\..\RL-ARM\Driver -I..\..\RL-ARM\RL-RTX\inc -I..\..\User\bsp\BSP -I..\..\RL-ARM\RL-CAN -I..\..\Libraries\DSP_LIB\Include -I..\..\MODBUS\modbus\rtu -I..\..\MODBUS\BARE\port -I..\..\MODBUS\modbus\include -I..\..\User\bsp\BSP -I..\..\PLC -I..\..\Avoid -I..\..\User\parameter -I..\..\User\LaserMotionCtr -I..\..\User\W5100S -I..\..\User\bsp -I..\..\User\CHASSIS -I..\..\User\CONTROLFUNCTION -I..\..\User\DATAUPDATE -I..\..\User\HARAWARE -I..\..\User\MOTORDRIVER -I..\..\User\NAVAGATION -I..\..\User\PLATFORM -I..\..\User\SENSOR -I.\RTE\_Flash -IC:\Users\YDJ\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include -IC:\Users\YDJ\AppData\Local\Arm\Packs\Keil\STM32F4xx_DFP\2.13.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include -D__UVISION_VERSION=527 -D_RTE_ -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -D__RTX -D__FPU_USED=1 --omf_browse=.\flash\obj\lib_mem.crf ..\..\uCOS-III\uC-LIB\lib_mem.c]
                          THUMB

                          AREA ||i.Mem_Clr||, CODE, READONLY, ALIGN=1

                  Mem_Clr PROC
;;;224    
;;;225    void  Mem_Clr (void        *pmem,
000000  460a              MOV      r2,r1
;;;226                   CPU_SIZE_T   size)
;;;227    {
;;;228        Mem_Set(pmem,
000002  2100              MOVS     r1,#0
000004  f7ffbffe          B.W      Mem_Set
;;;229                0u,                                                 /* See Note #2.                                         */
;;;230                size);
;;;231    }
;;;232    
                          ENDP


                          AREA ||i.Mem_Cmp||, CODE, READONLY, ALIGN=1

                  Mem_Cmp PROC
;;;620    /*$PAGE*/
;;;621    CPU_BOOLEAN  Mem_Cmp (const  void        *p1_mem,
000000  b570              PUSH     {r4-r6,lr}
;;;622                          const  void        *p2_mem,
;;;623                                 CPU_SIZE_T   size)
;;;624    {
000002  4603              MOV      r3,r0
;;;625               CPU_SIZE_T    size_rem;
;;;626               CPU_ALIGN    *p1_mem_align;
;;;627               CPU_ALIGN    *p2_mem_align;
;;;628        const  CPU_INT08U   *p1_mem_08;
;;;629        const  CPU_INT08U   *p2_mem_08;
;;;630               CPU_DATA      i;
;;;631               CPU_DATA      mem_align_mod_1;
;;;632               CPU_DATA      mem_align_mod_2;
;;;633               CPU_BOOLEAN   mem_aligned;
;;;634               CPU_BOOLEAN   mem_cmp;
;;;635    
;;;636    
;;;637        if (size < 1) {                                             /* See Note #1.                                         */
000004  2a00              CMP      r2,#0
000006  d00c              BEQ      |L2.34|
;;;638            return (DEF_YES);
;;;639        }
;;;640        if (p1_mem == (void *)0) {
000008  b16b              CBZ      r3,|L2.38|
;;;641            return (DEF_NO);
;;;642        }
;;;643        if (p2_mem == (void *)0) {
00000a  b171              CBZ      r1,|L2.42|
;;;644            return (DEF_NO);
;;;645        }
;;;646    
;;;647    
;;;648        mem_cmp         =  DEF_YES;                                 /* Assume mem bufs are identical until cmp fails.       */
00000c  2001              MOVS     r0,#1
;;;649        size_rem        =  size;
;;;650                                                                    /* Start @ end of mem bufs (see Note #2).               */
;;;651        p1_mem_08       = (const CPU_INT08U *)p1_mem + size;
00000e  4413              ADD      r3,r3,r2
;;;652        p2_mem_08       = (const CPU_INT08U *)p2_mem + size;
000010  4411              ADD      r1,r1,r2
;;;653                                                                    /* See Note #4.                                         */
;;;654        mem_align_mod_1 = (CPU_INT08U)((CPU_ADDR)p1_mem_08 % sizeof(CPU_ALIGN));
000012  f0030403          AND      r4,r3,#3
;;;655        mem_align_mod_2 = (CPU_INT08U)((CPU_ADDR)p2_mem_08 % sizeof(CPU_ALIGN));
000016  f0010503          AND      r5,r1,#3
;;;656    
;;;657        mem_aligned     = (mem_align_mod_1 == mem_align_mod_2) ? DEF_YES : DEF_NO;
00001a  42ac              CMP      r4,r5
00001c  d107              BNE      |L2.46|
00001e  2501              MOVS     r5,#1
000020  e006              B        |L2.48|
                  |L2.34|
000022  2001              MOVS     r0,#1                 ;638
;;;658    
;;;659        if (mem_aligned == DEF_YES) {                               /* If mem bufs' alignment offset equal, ...             */
;;;660                                                                    /* ... optimize cmp for mem buf alignment.              */
;;;661            if (mem_align_mod_1 != 0u) {                            /* If trailing octets avail,                  ...       */
;;;662                i = mem_align_mod_1;
;;;663                while ((mem_cmp == DEF_YES) &&                      /* ... cmp mem bufs while identical &         ...       */
;;;664                       (size_rem > 0)       &&                      /* ... start mem buf cmp with trailing octets ...       */
;;;665                       (i        > 0)) {                            /* ... until next CPU_ALIGN word boundary.              */
;;;666                    p1_mem_08--;
;;;667                    p2_mem_08--;
;;;668                    if (*p1_mem_08 != *p2_mem_08) {                 /* If ANY data octet(s) NOT identical, cmp fails.       */
;;;669                         mem_cmp = DEF_NO;
;;;670                    }
;;;671                    size_rem -= sizeof(CPU_INT08U);
;;;672                    i--;
;;;673                }
;;;674            }
;;;675    
;;;676            if (mem_cmp == DEF_YES) {                               /* If cmp still identical, cmp aligned mem bufs.        */
;;;677                p1_mem_align = (CPU_ALIGN *)p1_mem_08;              /* See Note #3a.                                        */
;;;678                p2_mem_align = (CPU_ALIGN *)p2_mem_08;
;;;679    
;;;680                while ((mem_cmp  == DEF_YES) &&                     /* Cmp mem bufs while identical & ...                   */
;;;681                       (size_rem >= sizeof(CPU_ALIGN))) {           /* ... mem bufs aligned on CPU_ALIGN word boundaries.   */
;;;682                    p1_mem_align--;
;;;683                    p2_mem_align--;
;;;684                    if (*p1_mem_align != *p2_mem_align) {           /* If ANY data octet(s) NOT identical, cmp fails.       */
;;;685                         mem_cmp = DEF_NO;
;;;686                    }
;;;687                    size_rem -= sizeof(CPU_ALIGN);
;;;688                }
;;;689    
;;;690                p1_mem_08 = (CPU_INT08U *)p1_mem_align;
;;;691                p2_mem_08 = (CPU_INT08U *)p2_mem_align;
;;;692            }
;;;693        }
;;;694    
;;;695        while ((mem_cmp == DEF_YES) &&                              /* Cmp mem bufs while identical ...                     */
;;;696               (size_rem > 0)) {                                    /* ... for unaligned mem bufs or trailing octets.       */
;;;697            p1_mem_08--;
;;;698            p2_mem_08--;
;;;699            if (*p1_mem_08 != *p2_mem_08) {                         /* If ANY data octet(s) NOT identical, cmp fails.       */
;;;700                 mem_cmp = DEF_NO;
;;;701            }
;;;702            size_rem -= sizeof(CPU_INT08U);
;;;703        }
;;;704    
;;;705        return (mem_cmp);
;;;706    }
000024  bd70              POP      {r4-r6,pc}
                  |L2.38|
000026  2000              MOVS     r0,#0                 ;641
000028  bd70              POP      {r4-r6,pc}
                  |L2.42|
00002a  2000              MOVS     r0,#0                 ;644
                  |L2.44|
00002c  bd70              POP      {r4-r6,pc}
                  |L2.46|
00002e  2500              MOVS     r5,#0                 ;657
                  |L2.48|
000030  2d01              CMP      r5,#1                 ;659
000032  d127              BNE      |L2.132|
000034  b94c              CBNZ     r4,|L2.74|
000036  e00d              B        |L2.84|
                  |L2.56|
000038  1e5b              SUBS     r3,r3,#1              ;666
00003a  1e49              SUBS     r1,r1,#1              ;667
00003c  781d              LDRB     r5,[r3,#0]            ;668
00003e  780e              LDRB     r6,[r1,#0]            ;668
000040  42b5              CMP      r5,r6                 ;668
000042  d000              BEQ      |L2.70|
000044  2000              MOVS     r0,#0                 ;669
                  |L2.70|
000046  1e52              SUBS     r2,r2,#1              ;671
000048  1e64              SUBS     r4,r4,#1              ;672
                  |L2.74|
00004a  2801              CMP      r0,#1                 ;663
00004c  d102              BNE      |L2.84|
00004e  b10a              CBZ      r2,|L2.84|
000050  2c00              CMP      r4,#0                 ;665
000052  d1f1              BNE      |L2.56|
                  |L2.84|
000054  2801              CMP      r0,#1                 ;676
000056  d008              BEQ      |L2.106|
000058  e014              B        |L2.132|
                  |L2.90|
00005a  1f1b              SUBS     r3,r3,#4              ;682
00005c  1f09              SUBS     r1,r1,#4              ;683
00005e  681c              LDR      r4,[r3,#0]            ;684
000060  680d              LDR      r5,[r1,#0]            ;684
000062  42ac              CMP      r4,r5                 ;684
000064  d000              BEQ      |L2.104|
000066  2000              MOVS     r0,#0                 ;685
                  |L2.104|
000068  1f12              SUBS     r2,r2,#4              ;687
                  |L2.106|
00006a  2801              CMP      r0,#1                 ;680
00006c  d10a              BNE      |L2.132|
00006e  2a04              CMP      r2,#4                 ;681
000070  d2f3              BCS      |L2.90|
000072  e007              B        |L2.132|
                  |L2.116|
000074  1e5b              SUBS     r3,r3,#1              ;697
000076  1e49              SUBS     r1,r1,#1              ;698
000078  781c              LDRB     r4,[r3,#0]            ;699
00007a  780d              LDRB     r5,[r1,#0]            ;699
00007c  42ac              CMP      r4,r5                 ;699
00007e  d000              BEQ      |L2.130|
000080  2000              MOVS     r0,#0                 ;700
                  |L2.130|
000082  1e52              SUBS     r2,r2,#1              ;702
                  |L2.132|
000084  2801              CMP      r0,#1                 ;695
000086  d1d1              BNE      |L2.44|
000088  2a00              CMP      r2,#0                 ;696
00008a  d1f3              BNE      |L2.116|
00008c  bd70              POP      {r4-r6,pc}
;;;707    
                          ENDP


                          AREA ||i.Mem_HeapAlloc||, CODE, READONLY, ALIGN=2

                  Mem_HeapAlloc PROC
;;;748    #if (LIB_MEM_CFG_ALLOC_EN == DEF_ENABLED)
;;;749    void  *Mem_HeapAlloc (CPU_SIZE_T   size,
000000  e92d5ffc          PUSH     {r2-r12,lr}
;;;750                          CPU_SIZE_T   align,
;;;751                          CPU_SIZE_T  *poctets_reqd,
;;;752                          LIB_ERR     *perr)
;;;753    {
000004  4681              MOV      r9,r0
000006  468b              MOV      r11,r1
000008  4615              MOV      r5,r2
00000a  461c              MOV      r4,r3
;;;754        MEM_POOL    *pmem_pool_heap;
;;;755        void        *pmem_addr;
;;;756        void        *pmem_blk;
;;;757        CPU_SIZE_T   octets_reqd_unused;
;;;758        CPU_SIZE_T   size_rem;
;;;759        CPU_SIZE_T   size_req;
;;;760        CPU_SR_ALLOC();
;;;761    
;;;762    
;;;763    #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)                     /* ------------- VALIDATE RTN ERR PTR ------------- */
;;;764        if (perr == (LIB_ERR *)0) {
00000c  2c00              CMP      r4,#0
00000e  d101              BNE      |L3.20|
;;;765            CPU_SW_EXCEPTION((void *)0);
000010  f7fffffe          BL       CPU_SW_Exception
                  |L3.20|
;;;766        }
;;;767    #endif
;;;768    
;;;769                                                                        /* ------------ VALIDATE RTN OCTETS PTR ----------- */
;;;770        if (poctets_reqd == (CPU_SIZE_T *) 0) {                         /* If NOT avail, ...                                */
000014  b905              CBNZ     r5,|L3.24|
;;;771            poctets_reqd  = (CPU_SIZE_T *)&octets_reqd_unused;          /* ... re-cfg NULL rtn ptr to unused local var.     */
000016  ad01              ADD      r5,sp,#4
                  |L3.24|
;;;772           (void)&octets_reqd_unused;                                   /* Prevent possible 'variable unused' warning.      */
;;;773        }
;;;774       *poctets_reqd = 0u;                                              /* Init octets req'd for err (see Note #1).         */
000018  2000              MOVS     r0,#0
00001a  6028              STR      r0,[r5,#0]
;;;775    
;;;776    
;;;777    #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)                     /* ------------ VALIDATE HEAP MEM ALLOC ----------- */
;;;778        if (size < 1) {
00001c  f1b90f00          CMP      r9,#0
000020  d020              BEQ      |L3.100|
;;;779           *perr = LIB_MEM_ERR_INVALID_MEM_SIZE;
;;;780            return ((void *)0);
;;;781        }
;;;782    
;;;783        if (align < 1) {
000022  f1bb0f00          CMP      r11,#0
000026  d022              BEQ      |L3.110|
;;;784           *perr = LIB_MEM_ERR_INVALID_MEM_ALIGN;
;;;785            return ((void *)0);
;;;786        }
;;;787    #endif
;;;788    
;;;789                                                                        /* -------------- ALLOC HEAP MEM BLK -------------- */
;;;790        pmem_pool_heap = &Mem_PoolHeap;
000028  4f24              LDR      r7,|L3.188|
;;;791    
;;;792        CPU_CRITICAL_ENTER();
00002a  f7fffffe          BL       CPU_SR_Save
00002e  9000              STR      r0,[sp,#0]
;;;793    
;;;794        pmem_addr = pmem_pool_heap->SegAddrNextAvail;
000030  6bf8              LDR      r0,[r7,#0x3c]
;;;795        size_rem  = pmem_pool_heap->SegSizeRem;
000032  f8d78044          LDR      r8,[r7,#0x44]
;;;796        size_req  = Mem_SegCalcTotSize(pmem_addr,
000036  465b              MOV      r3,r11
000038  464a              MOV      r2,r9
00003a  2101              MOVS     r1,#1
00003c  f7fffffe          BL       Mem_SegCalcTotSize
000040  4606              MOV      r6,r0
;;;797                                       1u,                              /* Calc alloc for single mem blk from heap.         */
;;;798                                       size,
;;;799                                       align);
;;;800    #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;801        if (size_req < 1) {                                             /* If req'd size ovf, ...                           */
000042  0030              MOVS     r0,r6
000044  d018              BEQ      |L3.120|
;;;802            CPU_CRITICAL_EXIT();
;;;803           *poctets_reqd = size;                                        /* ... rtn add'l heap size needed.                  */
;;;804           *perr         = LIB_MEM_ERR_HEAP_OVF;
;;;805            return ((void *)0);
;;;806        }
;;;807    #endif
;;;808    
;;;809        if (size_req > size_rem) {                                      /* If req'd size > rem heap size, ...               */
;;;810            CPU_CRITICAL_EXIT();
;;;811           *poctets_reqd = size_req - size_rem;                         /* ... rtn add'l heap size needed.                  */
;;;812           *perr         = LIB_MEM_ERR_HEAP_EMPTY;
000046  f2427ae2          MOV      r10,#0x27e2
00004a  4546              CMP      r6,r8                 ;809
00004c  d91e              BLS      |L3.140|
00004e  9800              LDR      r0,[sp,#0]            ;810
000050  f7fffffe          BL       CPU_SR_Restore
000054  eba60008          SUB      r0,r6,r8              ;811
000058  6028              STR      r0,[r5,#0]            ;811
00005a  f8a4a000          STRH     r10,[r4,#0]
;;;813            return ((void *)0);
00005e  2000              MOVS     r0,#0
                  |L3.96|
;;;814        }
;;;815    
;;;816        pmem_blk = Mem_SegAlloc(pmem_pool_heap, size, align);
;;;817        if (pmem_blk == (void *)0) {                                    /* If mem blk NOT avail from heap, ...              */
;;;818            CPU_CRITICAL_EXIT();
;;;819           *poctets_reqd = size_req;                                    /* ... rtn add'l heap size needed.                  */
;;;820           *perr         = LIB_MEM_ERR_HEAP_EMPTY;
;;;821            return ((void *)0);
;;;822        }
;;;823    
;;;824        CPU_CRITICAL_EXIT();
;;;825    
;;;826       *perr =  LIB_MEM_ERR_NONE;
;;;827    
;;;828        return (pmem_blk);
;;;829    }
000060  e8bd9ffc          POP      {r2-r12,pc}
                  |L3.100|
000064  f2427074          MOV      r0,#0x2774            ;779
000068  8020              STRH     r0,[r4,#0]            ;779
00006a  2000              MOVS     r0,#0                 ;780
00006c  e7f8              B        |L3.96|
                  |L3.110|
00006e  f2427075          MOV      r0,#0x2775            ;784
000072  8020              STRH     r0,[r4,#0]            ;784
000074  2000              MOVS     r0,#0                 ;785
000076  e7f3              B        |L3.96|
                  |L3.120|
000078  9800              LDR      r0,[sp,#0]            ;802
00007a  f7fffffe          BL       CPU_SR_Restore
00007e  f8c59000          STR      r9,[r5,#0]            ;803
000082  f24270e3          MOV      r0,#0x27e3            ;804
000086  8020              STRH     r0,[r4,#0]            ;804
000088  2000              MOVS     r0,#0                 ;805
00008a  e7e9              B        |L3.96|
                  |L3.140|
00008c  465a              MOV      r2,r11                ;816
00008e  4649              MOV      r1,r9                 ;816
000090  4638              MOV      r0,r7                 ;816
000092  f7fffffe          BL       Mem_SegAlloc
000096  4607              MOV      r7,r0                 ;816
000098  b13f              CBZ      r7,|L3.170|
00009a  9800              LDR      r0,[sp,#0]            ;824
00009c  f7fffffe          BL       CPU_SR_Restore
0000a0  f2427010          MOV      r0,#0x2710            ;826
0000a4  8020              STRH     r0,[r4,#0]            ;826
0000a6  4638              MOV      r0,r7                 ;828
0000a8  e7da              B        |L3.96|
                  |L3.170|
0000aa  9800              LDR      r0,[sp,#0]            ;818
0000ac  f7fffffe          BL       CPU_SR_Restore
0000b0  602e              STR      r6,[r5,#0]            ;819
0000b2  f8a4a000          STRH     r10,[r4,#0]           ;820
0000b6  2000              MOVS     r0,#0                 ;821
0000b8  e7d2              B        |L3.96|
;;;830    #endif
                          ENDP

0000ba  0000              DCW      0x0000
                  |L3.188|
                          DCD      ||.bss||

                          AREA ||i.Mem_HeapGetSizeRem||, CODE, READONLY, ALIGN=2

                  Mem_HeapGetSizeRem PROC
;;;861    #if (LIB_MEM_CFG_ALLOC_EN == DEF_ENABLED)
;;;862    CPU_SIZE_T  Mem_HeapGetSizeRem (CPU_SIZE_T   align,
000000  460a              MOV      r2,r1
;;;863                                    LIB_ERR     *perr)
;;;864    {
;;;865        CPU_SIZE_T  size_rem;
;;;866    
;;;867    
;;;868        size_rem = Mem_SegGetSizeRem(&Mem_PoolHeap, align, perr);
000002  4601              MOV      r1,r0
000004  4801              LDR      r0,|L4.12|
000006  f7ffbffe          B.W      Mem_SegGetSizeRem
;;;869    
;;;870        return (size_rem);
;;;871    }
;;;872    #endif
                          ENDP

00000a  0000              DCW      0x0000
                  |L4.12|
                          DCD      ||.bss||

                          AREA ||i.Mem_Init||, CODE, READONLY, ALIGN=2

                  Mem_Init PROC
;;;164    
;;;165    void  Mem_Init (void)
000000  480d              LDR      r0,|L5.56|
;;;166    {
;;;167    #if (LIB_MEM_CFG_ALLOC_EN == DEF_ENABLED)
;;;168        MEM_POOL  *pmem_pool;
;;;169    
;;;170                                                                            /* --------- INIT MEM HEAP SEG / POOL --------- */
;;;171        pmem_pool                   = (MEM_POOL   *)&Mem_PoolHeap;
;;;172        pmem_pool->Type             = (LIB_MEM_TYPE) LIB_MEM_TYPE_HEAP;
000002  490e              LDR      r1,|L5.60|
000004  6001              STR      r1,[r0,#0]
;;;173        pmem_pool->SegHeadPtr       = (MEM_POOL   *)&Mem_PoolHeap;          /* Heap seg head = heap seg.                    */
000006  4602              MOV      r2,r0
000008  6042              STR      r2,[r0,#4]
;;;174        pmem_pool->SegPrevPtr       = (MEM_POOL   *) 0;
00000a  2100              MOVS     r1,#0
00000c  6081              STR      r1,[r0,#8]
;;;175        pmem_pool->SegNextPtr       = (MEM_POOL   *) 0;
00000e  60c1              STR      r1,[r0,#0xc]
;;;176        pmem_pool->PoolPrevPtr      = (MEM_POOL   *) 0;
000010  6101              STR      r1,[r0,#0x10]
;;;177        pmem_pool->PoolNextPtr      = (MEM_POOL   *) 0;
000012  6141              STR      r1,[r0,#0x14]
;;;178        pmem_pool->PoolAddrStart    = (void       *) 0;
000014  6181              STR      r1,[r0,#0x18]
;;;179        pmem_pool->PoolAddrEnd      = (void       *) 0;
000016  61c1              STR      r1,[r0,#0x1c]
;;;180        pmem_pool->PoolPtrs         = (void      **) 0;
000018  6201              STR      r1,[r0,#0x20]
;;;181        pmem_pool->BlkSize          = (CPU_SIZE_T  ) 0u;
00001a  6301              STR      r1,[r0,#0x30]
;;;182        pmem_pool->BlkNbr           = (CPU_SIZE_T  ) 0u;
00001c  62c1              STR      r1,[r0,#0x2c]
;;;183        pmem_pool->BlkIx            = (MEM_POOL_IX ) 0u;
00001e  6241              STR      r1,[r0,#0x24]
;;;184    
;;;185    #ifdef  LIB_MEM_CFG_HEAP_BASE_ADDR
;;;186        pmem_pool->SegAddr          = (void       *) LIB_MEM_CFG_HEAP_BASE_ADDR;
;;;187        pmem_pool->SegAddrNextAvail = (void       *) LIB_MEM_CFG_HEAP_BASE_ADDR;
;;;188    #else
;;;189        pmem_pool->SegAddr          = (void       *)&Mem_Heap[0];
000020  f1000148          ADD      r1,r0,#0x48
000024  6381              STR      r1,[r0,#0x38]
;;;190        pmem_pool->SegAddrNextAvail = (void       *)&Mem_Heap[0];
000026  63c1              STR      r1,[r0,#0x3c]
;;;191    #endif
;;;192    
;;;193        pmem_pool->SegSizeTot       = (CPU_SIZE_T  ) LIB_MEM_CFG_HEAP_SIZE;
000028  f44f41b8          MOV      r1,#0x5c00
00002c  6401              STR      r1,[r0,#0x40]
;;;194        pmem_pool->SegSizeRem       = (CPU_SIZE_T  ) LIB_MEM_CFG_HEAP_SIZE;
00002e  6441              STR      r1,[r0,#0x44]
;;;195    
;;;196                                                                            /* ------------ INIT MEM POOL TBL ------------- */
;;;197        Mem_PoolTbl = &Mem_PoolHeap;
000030  4803              LDR      r0,|L5.64|
000032  6002              STR      r2,[r0,#0]  ; Mem_PoolTbl
;;;198    #endif
;;;199    }
000034  4770              BX       lr
;;;200    
                          ENDP

000036  0000              DCW      0x0000
                  |L5.56|
                          DCD      ||.bss||
                  |L5.60|
                          DCD      0x50414548
                  |L5.64|
                          DCD      ||.data||

                          AREA ||i.Mem_Move||, CODE, READONLY, ALIGN=1

                  Mem_Move PROC
;;;493    
;;;494    void  Mem_Move (       void        *pdest,
000000  b430              PUSH     {r4,r5}
;;;495                    const  void        *psrc,
;;;496                           CPU_SIZE_T   size)
;;;497    {
;;;498               CPU_SIZE_T    size_rem;
;;;499               CPU_SIZE_T    mem_gap_octets;
;;;500               CPU_ALIGN    *pmem_align_dest;
;;;501        const  CPU_ALIGN    *pmem_align_src;
;;;502               CPU_INT08U   *pmem_08_dest;
;;;503        const  CPU_INT08U   *pmem_08_src;
;;;504               CPU_INT08S    i;
;;;505               CPU_DATA      mem_align_mod_dest;
;;;506               CPU_DATA      mem_align_mod_src;
;;;507               CPU_BOOLEAN   mem_aligned;
;;;508    
;;;509    
;;;510    #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;511        if (size < 1) {
000002  2a00              CMP      r2,#0
000004  d03b              BEQ      |L6.126|
;;;512            return;
;;;513        }
;;;514        if (pdest == (void *)0) {
000006  2800              CMP      r0,#0
000008  d039              BEQ      |L6.126|
;;;515            return;
;;;516        }
;;;517        if (psrc  == (void *)0) {
00000a  2900              CMP      r1,#0
00000c  d037              BEQ      |L6.126|
;;;518            return;
;;;519        }
;;;520    #endif
;;;521    
;;;522        pmem_08_src  = (const CPU_INT08U *)psrc;
;;;523        pmem_08_dest = (      CPU_INT08U *)pdest;
;;;524        if (pmem_08_src > pmem_08_dest) {
00000e  4281              CMP      r1,r0
000010  d902              BLS      |L6.24|
;;;525            Mem_Copy(pdest, psrc, size);
000012  bc30              POP      {r4,r5}
000014  f7ffbffe          B.W      Mem_Copy
                  |L6.24|
;;;526            return;
;;;527        }
;;;528    
;;;529        size_rem           =  size;
;;;530    
;;;531        pmem_08_dest       = (      CPU_INT08U *)pdest + size - 1;
000018  1883              ADDS     r3,r0,r2
00001a  1e5b              SUBS     r3,r3,#1
;;;532        pmem_08_src        = (const CPU_INT08U *)psrc  + size - 1;
00001c  1888              ADDS     r0,r1,r2
00001e  1e40              SUBS     r0,r0,#1
;;;533        
;;;534        mem_gap_octets     = pmem_08_dest - pmem_08_src;
000020  1a19              SUBS     r1,r3,r0
;;;535        
;;;536    
;;;537        if (mem_gap_octets >= sizeof(CPU_ALIGN)) {                  /* Avoid bufs overlap.                                  */
000022  2904              CMP      r1,#4
000024  d329              BCC      |L6.122|
;;;538        
;;;539                                                                    /* See Note #4.                                         */
;;;540            mem_align_mod_dest = (CPU_INT08U)((CPU_ADDR)pmem_08_dest % sizeof(CPU_ALIGN));
000026  f0030103          AND      r1,r3,#3
;;;541            mem_align_mod_src  = (CPU_INT08U)((CPU_ADDR)pmem_08_src  % sizeof(CPU_ALIGN));
00002a  f0000403          AND      r4,r0,#3
;;;542    
;;;543            mem_aligned        = (mem_align_mod_dest == mem_align_mod_src) ? DEF_YES : DEF_NO;
00002e  42a1              CMP      r1,r4
000030  d101              BNE      |L6.54|
000032  2401              MOVS     r4,#1
000034  e000              B        |L6.56|
                  |L6.54|
000036  2400              MOVS     r4,#0
                  |L6.56|
;;;544    
;;;545            if (mem_aligned == DEF_YES) {                           /* If mem bufs' alignment offset equal, ...             */
000038  2c01              CMP      r4,#1
00003a  d11e              BNE      |L6.122|
;;;546                                                                    /* ... optimize copy for mem buf alignment.             */
;;;547                if (mem_align_mod_dest != (sizeof(CPU_ALIGN) - 1)) {/* If leading octets avail,                   ...       */
00003c  2903              CMP      r1,#3
00003e  d107              BNE      |L6.80|
000040  e009              B        |L6.86|
                  |L6.66|
;;;548                    i = mem_align_mod_dest;
;;;549                    while ((size_rem   >  0) &&                     /* ... start mem buf copy with leading octets ...       */
;;;550                           (i          >= 0)) {                     /* ... until next CPU_ALIGN word boundary.              */
;;;551                       *pmem_08_dest-- = *pmem_08_src--;
000042  f8104901          LDRB     r4,[r0],#-1
000046  f8034901          STRB     r4,[r3],#-1
;;;552                        size_rem      -=  sizeof(CPU_INT08U);
00004a  1e52              SUBS     r2,r2,#1
;;;553                        i--;
00004c  1e49              SUBS     r1,r1,#1
00004e  b249              SXTB     r1,r1
                  |L6.80|
000050  b10a              CBZ      r2,|L6.86|
000052  2900              CMP      r1,#0                 ;550
000054  daf5              BGE      |L6.66|
                  |L6.86|
;;;554                    }
;;;555                }
;;;556    
;;;557                                                                    /* See Note #3a.                                        */
;;;558                pmem_align_dest = (      CPU_ALIGN *)((CPU_INT08U *)pmem_08_dest - sizeof(CPU_ALIGN) + 1);
000056  1edb              SUBS     r3,r3,#3
;;;559                pmem_align_src  = (const CPU_ALIGN *)((CPU_INT08U *)pmem_08_src  - sizeof(CPU_ALIGN) + 1);
000058  1ec0              SUBS     r0,r0,#3
;;;560                while (size_rem      >=  sizeof(CPU_ALIGN)) {       /* While mem bufs aligned on CPU_ALIGN word boundaries, */
00005a  e004              B        |L6.102|
                  |L6.92|
;;;561                   *pmem_align_dest-- = *pmem_align_src--;          /* ... copy psrc to pdest with CPU_ALIGN-sized words.   */
00005c  f8501904          LDR      r1,[r0],#-4
000060  f8431904          STR      r1,[r3],#-4
;;;562                    size_rem         -=  sizeof(CPU_ALIGN);
000064  1f12              SUBS     r2,r2,#4
                  |L6.102|
000066  2a04              CMP      r2,#4                 ;560
000068  d2f8              BCS      |L6.92|
;;;563                }
;;;564    
;;;565                pmem_08_dest = (      CPU_INT08U *)pmem_align_dest + sizeof(CPU_ALIGN) - 1;
00006a  1cdb              ADDS     r3,r3,#3
;;;566                pmem_08_src  = (const CPU_INT08U *)pmem_align_src  + sizeof(CPU_ALIGN) - 1;
00006c  1cc0              ADDS     r0,r0,#3
00006e  e004              B        |L6.122|
                  |L6.112|
;;;567    
;;;568            }
;;;569        }
;;;570    
;;;571        while (size_rem > 0) {                                      /* For unaligned mem bufs or trailing octets, ...       */
;;;572           *pmem_08_dest-- = *pmem_08_src--;                        /* ... copy psrc to pdest by octets.                    */
000070  f8101901          LDRB     r1,[r0],#-1
000074  f8031901          STRB     r1,[r3],#-1
;;;573            size_rem      -=  sizeof(CPU_INT08U);
000078  1e52              SUBS     r2,r2,#1
                  |L6.122|
00007a  2a00              CMP      r2,#0                 ;571
00007c  d1f8              BNE      |L6.112|
                  |L6.126|
;;;574        }
;;;575    }
00007e  bc30              POP      {r4,r5}
000080  4770              BX       lr
;;;576    
                          ENDP


                          AREA ||i.Mem_PoolBlkFree||, CODE, READONLY, ALIGN=2

                  Mem_PoolBlkFree PROC
;;;1880   #if (LIB_MEM_CFG_ALLOC_EN == DEF_ENABLED)
;;;1881   void  Mem_PoolBlkFree (MEM_POOL  *pmem_pool,
000000  e92d41f0          PUSH     {r4-r8,lr}
;;;1882                          void      *pmem_blk,
;;;1883                          LIB_ERR   *perr)
;;;1884   {
000004  4604              MOV      r4,r0
000006  460e              MOV      r6,r1
000008  4615              MOV      r5,r2
;;;1885       void         *p_addr;
;;;1886       CPU_BOOLEAN   addr_valid;
;;;1887       MEM_POOL_IX   i;
;;;1888       CPU_SR_ALLOC();
;;;1889   
;;;1890   
;;;1891   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)                     /* ------------- VALIDATE RTN ERR PTR ------------- */
;;;1892       if (perr == (LIB_ERR *)0) {
00000a  2d00              CMP      r5,#0
00000c  d101              BNE      |L7.18|
;;;1893           CPU_SW_EXCEPTION(;);
00000e  f7fffffe          BL       CPU_SW_Exception
                  |L7.18|
;;;1894       }
;;;1895   #endif
;;;1896   
;;;1897                                                                       /* ------------ VALIDATE MEM POOL FREE ------------ */
;;;1898   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)                     /* Validate mem ptrs.                               */
;;;1899       if (pmem_pool == (MEM_POOL *)0) {
;;;1900          *perr = LIB_MEM_ERR_NULL_PTR;
000012  f2427011          MOV      r0,#0x2711
000016  b184              CBZ      r4,|L7.58|
;;;1901           return;
;;;1902       }
;;;1903   
;;;1904       if (pmem_blk == (void *)0) {
000018  b18e              CBZ      r6,|L7.62|
;;;1905          *perr = LIB_MEM_ERR_NULL_PTR;
;;;1906           return;
;;;1907       }
;;;1908   #endif
;;;1909   
;;;1910       CPU_CRITICAL_ENTER();
00001a  f7fffffe          BL       CPU_SR_Save
00001e  4607              MOV      r7,r0
;;;1911   
;;;1912   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;1913       if (pmem_pool->Type != LIB_MEM_TYPE_POOL) {                     /* Validate mem pool type.                          */
000020  4931              LDR      r1,|L7.232|
000022  6820              LDR      r0,[r4,#0]
;;;1914           CPU_CRITICAL_EXIT();
;;;1915          *perr = LIB_MEM_ERR_INVALID_POOL;
000024  f2427888          MOV      r8,#0x2788
000028  4288              CMP      r0,r1                 ;1913
00002a  d00a              BEQ      |L7.66|
00002c  4638              MOV      r0,r7                 ;1914
00002e  f7fffffe          BL       CPU_SR_Restore
000032  f8a58000          STRH     r8,[r5,#0]
                  |L7.54|
;;;1916           return;
;;;1917       }
;;;1918   
;;;1919       addr_valid = Mem_PoolBlkIsValidAddr(pmem_pool, pmem_blk);       /* Validate mem blk as valid pool blk addr.         */
;;;1920       if (addr_valid != DEF_OK) {
;;;1921           CPU_CRITICAL_EXIT();
;;;1922          *perr = LIB_MEM_ERR_INVALID_BLK_ADDR;
;;;1923           return;
;;;1924       }
;;;1925   
;;;1926       for (i = 0u; i < pmem_pool->BlkIx; i++) {                       /* Validate mem blk  NOT already in pool.           */
;;;1927           if (pmem_blk == pmem_pool->PoolPtrs[i]) {
;;;1928               CPU_CRITICAL_EXIT();
;;;1929              *perr = LIB_MEM_ERR_INVALID_BLK_ADDR_IN_POOL;
;;;1930               return;
;;;1931           }
;;;1932       }
;;;1933   #endif
;;;1934   
;;;1935       if (pmem_pool->BlkIx >= pmem_pool->BlkNbr) {                    /* Validate mem pool NOT already full.              */
;;;1936           CPU_CRITICAL_EXIT();
;;;1937          *perr = LIB_MEM_ERR_POOL_FULL;
;;;1938           return;
;;;1939       }
;;;1940   
;;;1941                                                                       /* ------------- FREE MEM BLK TO POOL ------------- */
;;;1942       addr_valid = DEF_NO;
;;;1943       for (i = pmem_pool->BlkIx; i < pmem_pool->BlkNbr; i++) {        /* Find ix of mem blk to free.                      */
;;;1944           p_addr = pmem_pool->PoolPtrs[i];
;;;1945           if (p_addr == pmem_blk) {
;;;1946               addr_valid = DEF_YES;
;;;1947               break;
;;;1948           }
;;;1949       }
;;;1950                                                                       /* Swap addr of mem blk to free in tbl.             */
;;;1951       if (addr_valid == DEF_YES) {
;;;1952           pmem_pool->PoolPtrs[i] = pmem_pool->PoolPtrs[pmem_pool->BlkIx];
;;;1953       } else {
;;;1954   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;1955           CPU_CRITICAL_EXIT();
;;;1956          *perr = LIB_MEM_ERR_INVALID_POOL;
;;;1957           return;
;;;1958   #endif
;;;1959       }
;;;1960   
;;;1961                                                                       /* Free mem blk.                                    */
;;;1962       pmem_pool->PoolPtrs[pmem_pool->BlkIx] = pmem_blk;
;;;1963       pmem_pool->BlkIx++;
;;;1964   
;;;1965       CPU_CRITICAL_EXIT();
;;;1966   
;;;1967      *perr = LIB_MEM_ERR_NONE;
;;;1968   }
000036  e8bd81f0          POP      {r4-r8,pc}
                  |L7.58|
00003a  8028              STRH     r0,[r5,#0]            ;1900
00003c  e7fb              B        |L7.54|
                  |L7.62|
00003e  8028              STRH     r0,[r5,#0]            ;1905
000040  e7f9              B        |L7.54|
                  |L7.66|
000042  4631              MOV      r1,r6                 ;1919
000044  4620              MOV      r0,r4                 ;1919
000046  f7fffffe          BL       Mem_PoolBlkIsValidAddr
00004a  2801              CMP      r0,#1                 ;1920
00004c  d006              BEQ      |L7.92|
00004e  4638              MOV      r0,r7                 ;1921
000050  f7fffffe          BL       CPU_SR_Restore
000054  f2427097          MOV      r0,#0x2797            ;1922
000058  8028              STRH     r0,[r5,#0]            ;1922
00005a  e7ec              B        |L7.54|
                  |L7.92|
00005c  2200              MOVS     r2,#0                 ;1926
00005e  6a63              LDR      r3,[r4,#0x24]         ;1926
000060  e00c              B        |L7.124|
                  |L7.98|
000062  6a20              LDR      r0,[r4,#0x20]         ;1927
000064  f8500022          LDR      r0,[r0,r2,LSL #2]     ;1927
000068  42b0              CMP      r0,r6                 ;1927
00006a  d106              BNE      |L7.122|
00006c  4638              MOV      r0,r7                 ;1928
00006e  f7fffffe          BL       CPU_SR_Restore
000072  f2427098          MOV      r0,#0x2798            ;1929
000076  8028              STRH     r0,[r5,#0]            ;1929
000078  e7dd              B        |L7.54|
                  |L7.122|
00007a  1c52              ADDS     r2,r2,#1              ;1926
                  |L7.124|
00007c  4293              CMP      r3,r2                 ;1926
00007e  d8f0              BHI      |L7.98|
000080  f8d4c02c          LDR      r12,[r4,#0x2c]        ;1935
000084  4563              CMP      r3,r12                ;1935
000086  d306              BCC      |L7.150|
000088  4638              MOV      r0,r7                 ;1936
00008a  f7fffffe          BL       CPU_SR_Restore
00008e  f24270dd          MOV      r0,#0x27dd            ;1937
000092  8028              STRH     r0,[r5,#0]            ;1937
000094  e7cf              B        |L7.54|
                  |L7.150|
000096  2200              MOVS     r2,#0                 ;1942
000098  4618              MOV      r0,r3                 ;1943
00009a  e007              B        |L7.172|
                  |L7.156|
00009c  6a21              LDR      r1,[r4,#0x20]         ;1944
00009e  f8511020          LDR      r1,[r1,r0,LSL #2]     ;1944
0000a2  42b1              CMP      r1,r6                 ;1945
0000a4  d101              BNE      |L7.170|
0000a6  2201              MOVS     r2,#1                 ;1946
0000a8  e002              B        |L7.176|
                  |L7.170|
0000aa  1c40              ADDS     r0,r0,#1              ;1943
                  |L7.172|
0000ac  4584              CMP      r12,r0                ;1943
0000ae  d8f5              BHI      |L7.156|
                  |L7.176|
0000b0  2a01              CMP      r2,#1                 ;1951
0000b2  d005              BEQ      |L7.192|
0000b4  4638              MOV      r0,r7                 ;1955
0000b6  f7fffffe          BL       CPU_SR_Restore
0000ba  f8a58000          STRH     r8,[r5,#0]            ;1956
0000be  e7ba              B        |L7.54|
                  |L7.192|
0000c0  6a21              LDR      r1,[r4,#0x20]         ;1952
0000c2  f8512023          LDR      r2,[r1,r3,LSL #2]     ;1952
0000c6  f8412020          STR      r2,[r1,r0,LSL #2]     ;1952
0000ca  e9d40108          LDRD     r0,r1,[r4,#0x20]      ;1962
0000ce  f8406021          STR      r6,[r0,r1,LSL #2]     ;1962
0000d2  6a60              LDR      r0,[r4,#0x24]         ;1963
0000d4  1c40              ADDS     r0,r0,#1              ;1963
0000d6  6260              STR      r0,[r4,#0x24]         ;1963
0000d8  4638              MOV      r0,r7                 ;1965
0000da  f7fffffe          BL       CPU_SR_Restore
0000de  f2427010          MOV      r0,#0x2710            ;1967
0000e2  8028              STRH     r0,[r5,#0]            ;1967
0000e4  e7a7              B        |L7.54|
;;;1969   #endif
                          ENDP

0000e6  0000              DCW      0x0000
                  |L7.232|
                          DCD      0x4c4f4f50

                          AREA ||i.Mem_PoolBlkGet||, CODE, READONLY, ALIGN=2

                  Mem_PoolBlkGet PROC
;;;1678   #if (LIB_MEM_CFG_ALLOC_EN == DEF_ENABLED)
;;;1679   void  *Mem_PoolBlkGet (MEM_POOL    *pmem_pool,
000000  e92d41f0          PUSH     {r4-r8,lr}
;;;1680                          CPU_SIZE_T   size,
;;;1681                          LIB_ERR     *perr)
;;;1682   {
000004  4605              MOV      r5,r0
000006  460e              MOV      r6,r1
000008  4614              MOV      r4,r2
;;;1683       void  *pmem_blk;
;;;1684       CPU_SR_ALLOC();
;;;1685   
;;;1686   
;;;1687   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)                     /* ------------- VALIDATE RTN ERR PTR ------------- */
;;;1688       if (perr == (LIB_ERR *)0) {
00000a  2c00              CMP      r4,#0
00000c  d101              BNE      |L8.18|
;;;1689           CPU_SW_EXCEPTION((void *)0);
00000e  f7fffffe          BL       CPU_SW_Exception
                  |L8.18|
;;;1690       }
;;;1691   #endif
;;;1692   
;;;1693                                                                       /* ------------ VALIDATE MEM POOL GET ------------- */
;;;1694   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;1695       if (pmem_pool == (MEM_POOL *)0) {                               /* Validate mem ptr.                                */
000012  b185              CBZ      r5,|L8.54|
;;;1696          *perr = LIB_MEM_ERR_NULL_PTR;
;;;1697           return ((void *)0);
;;;1698       }
;;;1699   
;;;1700       if (size < 1) {                                                 /* Validate req'd size as non-NULL.                 */
;;;1701          *perr = LIB_MEM_ERR_INVALID_BLK_SIZE;
000014  f2427793          MOV      r7,#0x2793
000018  b196              CBZ      r6,|L8.64|
;;;1702           return ((void *)0);
;;;1703       }
;;;1704   #endif
;;;1705   
;;;1706       CPU_CRITICAL_ENTER();
00001a  f7fffffe          BL       CPU_SR_Save
;;;1707   
;;;1708   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;1709       if (pmem_pool->Type != LIB_MEM_TYPE_POOL) {                     /* Validate mem pool type.                          */
00001e  4a1d              LDR      r2,|L8.148|
000020  6829              LDR      r1,[r5,#0]
000022  4291              CMP      r1,r2
000024  d00f              BEQ      |L8.70|
;;;1710           CPU_CRITICAL_EXIT();
000026  f7fffffe          BL       CPU_SR_Restore
;;;1711          *perr = LIB_MEM_ERR_INVALID_POOL;
00002a  f2427088          MOV      r0,#0x2788
00002e  8020              STRH     r0,[r4,#0]
;;;1712           return ((void *)0);
000030  2000              MOVS     r0,#0
                  |L8.50|
;;;1713       }
;;;1714   
;;;1715       if (size > pmem_pool->BlkSize) {                                /* Validate req'd size <= mem pool blk size.        */
;;;1716           CPU_CRITICAL_EXIT();
;;;1717          *perr = LIB_MEM_ERR_INVALID_BLK_SIZE;
;;;1718           return ((void *)0);
;;;1719       }
;;;1720   #endif
;;;1721   
;;;1722      (void)&size;                                                     /* Prevent possible 'variable unused' warning.      */
;;;1723   
;;;1724       if (pmem_pool->BlkIx < 1) {                                     /* Validate mem pool as NOT empty.                  */
;;;1725           CPU_CRITICAL_EXIT();
;;;1726          *perr = LIB_MEM_ERR_POOL_EMPTY;
;;;1727           return ((void *)0);
;;;1728       }
;;;1729   
;;;1730       if (pmem_pool->BlkIx > pmem_pool->BlkNbr) {                     /* Validate mem pool ix NOT corrupt.                */
;;;1731           CPU_CRITICAL_EXIT();
;;;1732          *perr = LIB_MEM_ERR_INVALID_BLK_IX;
;;;1733           return ((void *)0);
;;;1734       }
;;;1735   
;;;1736                                                                       /* ------------ GET MEM BLK FROM POOL ------------- */
;;;1737       pmem_pool->BlkIx--;
;;;1738       pmem_blk = pmem_pool->PoolPtrs[pmem_pool->BlkIx];
;;;1739   
;;;1740       CPU_CRITICAL_EXIT();
;;;1741   
;;;1742      *perr =  LIB_MEM_ERR_NONE;
;;;1743   
;;;1744       return (pmem_blk);
;;;1745   }
000032  e8bd81f0          POP      {r4-r8,pc}
                  |L8.54|
000036  f2427011          MOV      r0,#0x2711            ;1696
00003a  8020              STRH     r0,[r4,#0]            ;1696
00003c  2000              MOVS     r0,#0                 ;1697
00003e  e7f8              B        |L8.50|
                  |L8.64|
000040  8027              STRH     r7,[r4,#0]            ;1701
000042  2000              MOVS     r0,#0                 ;1702
000044  e7f5              B        |L8.50|
                  |L8.70|
000046  6b29              LDR      r1,[r5,#0x30]         ;1715
000048  42b1              CMP      r1,r6                 ;1715
00004a  d204              BCS      |L8.86|
00004c  f7fffffe          BL       CPU_SR_Restore
000050  8027              STRH     r7,[r4,#0]            ;1717
000052  2000              MOVS     r0,#0                 ;1718
000054  e7ed              B        |L8.50|
                  |L8.86|
000056  6a69              LDR      r1,[r5,#0x24]         ;1724
000058  b149              CBZ      r1,|L8.110|
00005a  6aea              LDR      r2,[r5,#0x2c]         ;1730
00005c  4291              CMP      r1,r2                 ;1730
00005e  d90d              BLS      |L8.124|
000060  f7fffffe          BL       CPU_SR_Restore
000064  f2427095          MOV      r0,#0x2795            ;1732
000068  8020              STRH     r0,[r4,#0]            ;1732
00006a  2000              MOVS     r0,#0                 ;1733
00006c  e7e1              B        |L8.50|
                  |L8.110|
00006e  f7fffffe          BL       CPU_SR_Restore
000072  f24270de          MOV      r0,#0x27de            ;1726
000076  8020              STRH     r0,[r4,#0]            ;1726
000078  2000              MOVS     r0,#0                 ;1727
00007a  e7da              B        |L8.50|
                  |L8.124|
00007c  1e49              SUBS     r1,r1,#1              ;1737
00007e  6269              STR      r1,[r5,#0x24]         ;1737
000080  6a2a              LDR      r2,[r5,#0x20]         ;1738
000082  f8525021          LDR      r5,[r2,r1,LSL #2]     ;1738
000086  f7fffffe          BL       CPU_SR_Restore
00008a  f2427010          MOV      r0,#0x2710            ;1742
00008e  8020              STRH     r0,[r4,#0]            ;1742
000090  4628              MOV      r0,r5                 ;1744
000092  e7ce              B        |L8.50|
;;;1746   #endif
                          ENDP

                  |L8.148|
                          DCD      0x4c4f4f50

                          AREA ||i.Mem_PoolBlkGetNbrAvail||, CODE, READONLY, ALIGN=2

                  Mem_PoolBlkGetNbrAvail PROC
;;;1597   #if (LIB_MEM_CFG_ALLOC_EN == DEF_ENABLED)
;;;1598   MEM_POOL_BLK_QTY  Mem_PoolBlkGetNbrAvail (MEM_POOL  *pmem_pool,
000000  b570              PUSH     {r4-r6,lr}
;;;1599                                             LIB_ERR   *perr)
;;;1600   {
000002  4605              MOV      r5,r0
000004  460c              MOV      r4,r1
;;;1601       MEM_POOL_BLK_QTY  nbr_blk_rem;
;;;1602       CPU_SR_ALLOC();
;;;1603   
;;;1604   
;;;1605   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;1606                                                                   /* --------------- VALIDATE RTN ERR PTR --------------- */
;;;1607       if (perr == (LIB_ERR *)0) {
000006  2c00              CMP      r4,#0
000008  d101              BNE      |L9.14|
;;;1608           CPU_SW_EXCEPTION(0u);
00000a  f7fffffe          BL       CPU_SW_Exception
                  |L9.14|
;;;1609       }
;;;1610                                                                   /* ---------------- VALIDATE MEM POOL ----------------- */
;;;1611       if (pmem_pool == (MEM_POOL *)0) {                           /* Validate mem ptr.                                    */
00000e  b165              CBZ      r5,|L9.42|
;;;1612          *perr =  LIB_MEM_ERR_NULL_PTR;
;;;1613           return (0u);
;;;1614       }
;;;1615   #endif
;;;1616   
;;;1617       CPU_CRITICAL_ENTER();
000010  f7fffffe          BL       CPU_SR_Save
;;;1618   
;;;1619   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;1620       switch (pmem_pool->Type) {                                  /* Validate mem pool type.                              */
000014  4a0b              LDR      r2,|L9.68|
000016  6829              LDR      r1,[r5,#0]
000018  42d1              CMN      r1,r2
00001a  d00b              BEQ      |L9.52|
;;;1621           case LIB_MEM_TYPE_POOL:
;;;1622                break;
;;;1623   
;;;1624   
;;;1625           case LIB_MEM_TYPE_NONE:
;;;1626           case LIB_MEM_TYPE_HEAP:
;;;1627           default:
;;;1628                CPU_CRITICAL_EXIT();
00001c  f7fffffe          BL       CPU_SR_Restore
;;;1629               *perr =  LIB_MEM_ERR_INVALID_POOL;
000020  f2427088          MOV      r0,#0x2788
000024  8020              STRH     r0,[r4,#0]
;;;1630                return (0u);                                       /* Prevent 'break NOT reachable' compiler warning.      */
000026  2000              MOVS     r0,#0
;;;1631       }
;;;1632   #endif
;;;1633   
;;;1634                                                                   /* --------- GET REM'ING MEM POOL NBR BLK(S) ---------- */
;;;1635       nbr_blk_rem = pmem_pool->BlkIx;
;;;1636   
;;;1637       CPU_CRITICAL_EXIT();
;;;1638   
;;;1639   
;;;1640      *perr =  LIB_MEM_ERR_NONE;
;;;1641   
;;;1642       return (nbr_blk_rem);
;;;1643   }
000028  bd70              POP      {r4-r6,pc}
                  |L9.42|
00002a  f2427011          MOV      r0,#0x2711            ;1612
00002e  8020              STRH     r0,[r4,#0]            ;1612
000030  2000              MOVS     r0,#0                 ;1613
000032  bd70              POP      {r4-r6,pc}
                  |L9.52|
000034  6a6d              LDR      r5,[r5,#0x24]         ;1635
000036  f7fffffe          BL       CPU_SR_Restore
00003a  f2427010          MOV      r0,#0x2710            ;1640
00003e  8020              STRH     r0,[r4,#0]            ;1640
000040  4628              MOV      r0,r5                 ;1642
000042  bd70              POP      {r4-r6,pc}
;;;1644   #endif
                          ENDP

                  |L9.68|
                          DCD      0xb3b0b0b0

                          AREA ||i.Mem_PoolBlkGetUsedAtIx||, CODE, READONLY, ALIGN=2

                  Mem_PoolBlkGetUsedAtIx PROC
;;;1783   #if (LIB_MEM_CFG_ALLOC_EN == DEF_ENABLED)
;;;1784   void  *Mem_PoolBlkGetUsedAtIx (MEM_POOL          *pmem_pool,
000000  e92d41f0          PUSH     {r4-r8,lr}
;;;1785                                  MEM_POOL_IX        used_ix,
;;;1786                                  LIB_ERR           *perr)
;;;1787   {
000004  4605              MOV      r5,r0
000006  460f              MOV      r7,r1
000008  4614              MOV      r4,r2
;;;1788       MEM_POOL_IX   blk_ix;
;;;1789       void         *pmem_blk;
;;;1790       CPU_SR_ALLOC();
;;;1791   
;;;1792   
;;;1793   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)                     /* ------------- VALIDATE RTN ERR PTR ------------- */
;;;1794       if (perr == (LIB_ERR *)0) {
00000a  2c00              CMP      r4,#0
00000c  d101              BNE      |L10.18|
;;;1795           CPU_SW_EXCEPTION((void *)0);
00000e  f7fffffe          BL       CPU_SW_Exception
                  |L10.18|
;;;1796       }
;;;1797   #endif
;;;1798   
;;;1799                                                                       /* ------------ VALIDATE MEM POOL GET ------------- */
;;;1800   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;1801       if (pmem_pool == (MEM_POOL *)0) {                               /* Validate mem ptr.                                */
000012  b16d              CBZ      r5,|L10.48|
;;;1802          *perr = LIB_MEM_ERR_NULL_PTR;
;;;1803           return ((void *)0);
;;;1804       }
;;;1805   #endif
;;;1806   
;;;1807       CPU_CRITICAL_ENTER();
000014  f7fffffe          BL       CPU_SR_Save
;;;1808   
;;;1809   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;1810       if (pmem_pool->Type != LIB_MEM_TYPE_POOL) {                     /* Validate mem pool type.                          */
000018  4a1a              LDR      r2,|L10.132|
00001a  6829              LDR      r1,[r5,#0]
00001c  4291              CMP      r1,r2
00001e  d00c              BEQ      |L10.58|
;;;1811           CPU_CRITICAL_EXIT();
000020  f7fffffe          BL       CPU_SR_Restore
;;;1812          *perr = LIB_MEM_ERR_INVALID_POOL;
000024  f2427088          MOV      r0,#0x2788
000028  8020              STRH     r0,[r4,#0]
;;;1813           return ((void *)0);
00002a  2000              MOVS     r0,#0
                  |L10.44|
;;;1814       }
;;;1815   
;;;1816       if (pmem_pool->BlkIx >= pmem_pool->BlkNbr) {                    /* Validate mem pool as NOT full.                   */
;;;1817           CPU_CRITICAL_EXIT();
;;;1818          *perr = LIB_MEM_ERR_INVALID_BLK_IX;
;;;1819           return ((void *)0);
;;;1820       }
;;;1821   #endif
;;;1822   
;;;1823       blk_ix = pmem_pool->BlkNbr - used_ix - 1u;
;;;1824   
;;;1825       if (blk_ix >= pmem_pool->BlkNbr) {                              /* Validate ix range.                               */
;;;1826           CPU_CRITICAL_EXIT();
;;;1827          *perr = LIB_MEM_ERR_INVALID_BLK_IX;
;;;1828           return ((void *)0);
;;;1829       }
;;;1830   
;;;1831       if (blk_ix < pmem_pool->BlkIx) {
;;;1832           CPU_CRITICAL_EXIT();
;;;1833          *perr = LIB_MEM_ERR_INVALID_BLK_IX;
;;;1834           return ((void *)0);
;;;1835       }
;;;1836                                                                       /* ------------ GET MEM BLK FROM POOL ------------- */
;;;1837       pmem_blk = pmem_pool->PoolPtrs[blk_ix];
;;;1838   
;;;1839       CPU_CRITICAL_EXIT();
;;;1840   
;;;1841      *perr =  LIB_MEM_ERR_NONE;
;;;1842   
;;;1843       return (pmem_blk);
;;;1844   }
00002c  e8bd81f0          POP      {r4-r8,pc}
                  |L10.48|
000030  f2427011          MOV      r0,#0x2711            ;1802
000034  8020              STRH     r0,[r4,#0]            ;1802
000036  2000              MOVS     r0,#0                 ;1803
000038  e7f8              B        |L10.44|
                  |L10.58|
00003a  6a6b              LDR      r3,[r5,#0x24]         ;1816
00003c  6aea              LDR      r2,[r5,#0x2c]         ;1816
00003e  f2427695          MOV      r6,#0x2795            ;1818
000042  4293              CMP      r3,r2                 ;1816
000044  d304              BCC      |L10.80|
000046  f7fffffe          BL       CPU_SR_Restore
00004a  8026              STRH     r6,[r4,#0]            ;1818
00004c  2000              MOVS     r0,#0                 ;1819
00004e  e7ed              B        |L10.44|
                  |L10.80|
000050  1bd1              SUBS     r1,r2,r7              ;1823
000052  1e49              SUBS     r1,r1,#1              ;1823
000054  428a              CMP      r2,r1                 ;1825
000056  d804              BHI      |L10.98|
000058  f7fffffe          BL       CPU_SR_Restore
00005c  8026              STRH     r6,[r4,#0]            ;1827
00005e  2000              MOVS     r0,#0                 ;1828
000060  e7e4              B        |L10.44|
                  |L10.98|
000062  428b              CMP      r3,r1                 ;1831
000064  d904              BLS      |L10.112|
000066  f7fffffe          BL       CPU_SR_Restore
00006a  8026              STRH     r6,[r4,#0]            ;1833
00006c  2000              MOVS     r0,#0                 ;1834
00006e  e7dd              B        |L10.44|
                  |L10.112|
000070  6a2a              LDR      r2,[r5,#0x20]         ;1837
000072  f8525021          LDR      r5,[r2,r1,LSL #2]     ;1837
000076  f7fffffe          BL       CPU_SR_Restore
00007a  f2427010          MOV      r0,#0x2710            ;1841
00007e  8020              STRH     r0,[r4,#0]            ;1841
000080  4628              MOV      r0,r5                 ;1843
000082  e7d3              B        |L10.44|
;;;1845   #endif
                          ENDP

                  |L10.132|
                          DCD      0x4c4f4f50

                          AREA ||i.Mem_PoolBlkIsValidAddr||, CODE, READONLY, ALIGN=1

                  Mem_PoolBlkIsValidAddr PROC
;;;2128        (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED))
;;;2129   static  CPU_BOOLEAN  Mem_PoolBlkIsValidAddr (MEM_POOL  *pmem_pool,
000000  b530              PUSH     {r4,r5,lr}
;;;2130                                                void      *pmem_blk)
;;;2131   {
;;;2132       CPU_INT08U   *ppool_addr_first;
;;;2133       void         *ppool_addr_start;
;;;2134       void         *ppool_addr_end;
;;;2135       CPU_SIZE_T    align_offset;
;;;2136       CPU_SIZE_T    blk_align;
;;;2137       CPU_SIZE_T    blk_align_offset;
;;;2138       CPU_SIZE_T    blk_size;
;;;2139       CPU_SIZE_T    mem_align;
;;;2140       CPU_SIZE_T    mem_align_offset;
;;;2141       CPU_SIZE_T    mem_diff;
;;;2142       CPU_BOOLEAN   addr_valid;
;;;2143   
;;;2144   
;;;2145       ppool_addr_start = pmem_pool->PoolAddrStart;
000002  6983              LDR      r3,[r0,#0x18]
;;;2146       ppool_addr_end   = pmem_pool->PoolAddrEnd;
000004  69c2              LDR      r2,[r0,#0x1c]
;;;2147   
;;;2148       if ((pmem_blk < ppool_addr_start) ||
000006  4299              CMP      r1,r3
000008  d301              BCC      |L11.14|
;;;2149           (pmem_blk > ppool_addr_end)) {
00000a  4291              CMP      r1,r2
00000c  d901              BLS      |L11.18|
                  |L11.14|
;;;2150           return (DEF_NO);
00000e  2000              MOVS     r0,#0
;;;2151       }
;;;2152   
;;;2153       blk_align      = (CPU_SIZE_T)pmem_pool->BlkAlign;
;;;2154       align_offset   = (CPU_SIZE_T)((CPU_ADDR)ppool_addr_start % blk_align);
;;;2155       if (align_offset != 0u) {
;;;2156           mem_align_offset = blk_align - align_offset;
;;;2157       } else {
;;;2158           mem_align_offset = 0u;
;;;2159       }
;;;2160   
;;;2161       blk_size     = pmem_pool->BlkSize;
;;;2162       align_offset = blk_size % blk_align;
;;;2163       if (align_offset != 0u) {
;;;2164           blk_align_offset = blk_align - align_offset;
;;;2165       } else {
;;;2166           blk_align_offset = 0u;
;;;2167       }
;;;2168   
;;;2169       ppool_addr_first = (CPU_INT08U *)((CPU_INT08U *)ppool_addr_start + mem_align_offset);
;;;2170       mem_diff         = (CPU_SIZE_T  )((CPU_INT08U *)pmem_blk         - ppool_addr_first);
;;;2171       mem_align        = (CPU_SIZE_T  )(              blk_size         + blk_align_offset);
;;;2172   
;;;2173       addr_valid       = ((mem_diff % mem_align) == 0u) ? DEF_YES : DEF_NO;
;;;2174   
;;;2175       return (addr_valid);
;;;2176   }
000010  bd30              POP      {r4,r5,pc}
                  |L11.18|
000012  6b42              LDR      r2,[r0,#0x34]         ;2153
000014  fbb3f4f2          UDIV     r4,r3,r2              ;2154
000018  fb023414          MLS      r4,r2,r4,r3           ;2154
00001c  b10c              CBZ      r4,|L11.34|
00001e  1b14              SUBS     r4,r2,r4              ;2156
000020  e000              B        |L11.36|
                  |L11.34|
000022  2400              MOVS     r4,#0                 ;2158
                  |L11.36|
000024  6b00              LDR      r0,[r0,#0x30]         ;2161
000026  fbb0f5f2          UDIV     r5,r0,r2              ;2162
00002a  fb020515          MLS      r5,r2,r5,r0           ;2162
00002e  b10d              CBZ      r5,|L11.52|
000030  1b52              SUBS     r2,r2,r5              ;2164
000032  e000              B        |L11.54|
                  |L11.52|
000034  2200              MOVS     r2,#0                 ;2166
                  |L11.54|
000036  4423              ADD      r3,r3,r4              ;2169
000038  1ac9              SUBS     r1,r1,r3              ;2170
00003a  4410              ADD      r0,r0,r2              ;2171
00003c  fbb1f2f0          UDIV     r2,r1,r0              ;2173
000040  fb001012          MLS      r0,r0,r2,r1           ;2173
000044  b108              CBZ      r0,|L11.74|
000046  2000              MOVS     r0,#0                 ;2173
000048  bd30              POP      {r4,r5,pc}
                  |L11.74|
00004a  2001              MOVS     r0,#1                 ;2173
00004c  bd30              POP      {r4,r5,pc}
;;;2177   #endif
                          ENDP


                          AREA ||i.Mem_PoolBlkIxGet||, CODE, READONLY, ALIGN=2

                  Mem_PoolBlkIxGet PROC
;;;2008   #if (LIB_MEM_CFG_ALLOC_EN == DEF_ENABLED)
;;;2009   MEM_POOL_IX  Mem_PoolBlkIxGet (MEM_POOL  *pmem_pool,
000000  e92d47f0          PUSH     {r4-r10,lr}
;;;2010                                  void      *pmem_blk,
;;;2011                                  LIB_ERR   *perr)
;;;2012   {
000004  4605              MOV      r5,r0
000006  460e              MOV      r6,r1
000008  4614              MOV      r4,r2
;;;2013       void         *p_addr;
;;;2014       CPU_BOOLEAN   addr_valid;
;;;2015       MEM_POOL_IX   i;
;;;2016       MEM_POOL_IX   pool_ix;
;;;2017       MEM_POOL_IX   invalid_ix;
;;;2018       CPU_SR_ALLOC();
;;;2019   
;;;2020   
;;;2021       invalid_ix = DEF_GET_U_MAX_VAL(MEM_POOL_IX);
00000a  f04f39ff          MOV      r9,#0xffffffff
;;;2022   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)                     /* ------------- VALIDATE RTN ERR PTR ------------- */
;;;2023       if (perr == (LIB_ERR *)0) {
00000e  2c00              CMP      r4,#0
000010  d101              BNE      |L12.22|
;;;2024           CPU_SW_EXCEPTION(invalid_ix);
000012  f7fffffe          BL       CPU_SW_Exception
                  |L12.22|
;;;2025       }
;;;2026   #endif
;;;2027   
;;;2028                                                                       /* ------------ VALIDATE MEM POOL FREE ------------ */
;;;2029   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)                     /* Validate mem ptrs.                               */
;;;2030       if (pmem_pool == (MEM_POOL *)0) {
;;;2031          *perr = LIB_MEM_ERR_NULL_PTR;
000016  f2427011          MOV      r0,#0x2711
00001a  b18d              CBZ      r5,|L12.64|
;;;2032           return (invalid_ix);
;;;2033       }
;;;2034   
;;;2035       if (pmem_blk == (void *)0) {
00001c  b19e              CBZ      r6,|L12.70|
;;;2036          *perr = LIB_MEM_ERR_NULL_PTR;
;;;2037           return (invalid_ix);
;;;2038       }
;;;2039   #endif
;;;2040   
;;;2041       CPU_CRITICAL_ENTER();
00001e  f7fffffe          BL       CPU_SR_Save
000022  4607              MOV      r7,r0
;;;2042   
;;;2043   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;2044       if (pmem_pool->Type != LIB_MEM_TYPE_POOL) {                     /* Validate mem pool type.                          */
000024  492f              LDR      r1,|L12.228|
000026  6828              LDR      r0,[r5,#0]
;;;2045           CPU_CRITICAL_EXIT();
;;;2046          *perr = LIB_MEM_ERR_INVALID_POOL;
000028  f2427888          MOV      r8,#0x2788
00002c  4288              CMP      r0,r1                 ;2044
00002e  d00d              BEQ      |L12.76|
000030  4638              MOV      r0,r7                 ;2045
000032  f7fffffe          BL       CPU_SR_Restore
000036  f8a48000          STRH     r8,[r4,#0]
;;;2047           return(invalid_ix);
00003a  4648              MOV      r0,r9
                  |L12.60|
;;;2048       }
;;;2049   
;;;2050       addr_valid = Mem_PoolBlkIsValidAddr(pmem_pool, pmem_blk);       /* Validate mem blk as valid pool blk addr.         */
;;;2051       if (addr_valid != DEF_OK) {
;;;2052           CPU_CRITICAL_EXIT();
;;;2053          *perr = LIB_MEM_ERR_INVALID_BLK_ADDR;
;;;2054           return (invalid_ix);
;;;2055       }
;;;2056   
;;;2057       for (i = 0u; i < pmem_pool->BlkIx; i++) {                       /* Validate mem blk  NOT already in pool.           */
;;;2058           if (pmem_blk == pmem_pool->PoolPtrs[i]) {
;;;2059               CPU_CRITICAL_EXIT();
;;;2060              *perr = LIB_MEM_ERR_INVALID_BLK_ADDR_IN_POOL;
;;;2061               return (invalid_ix);
;;;2062           }
;;;2063       }
;;;2064   #endif
;;;2065   
;;;2066       if (pmem_pool->BlkIx >= pmem_pool->BlkNbr) {                    /* Validate mem pool NOT full.                      */
;;;2067           CPU_CRITICAL_EXIT();
;;;2068          *perr = LIB_MEM_ERR_POOL_FULL;
;;;2069           return (invalid_ix);
;;;2070       }
;;;2071   
;;;2072       addr_valid = DEF_NO;
;;;2073       for (i = pmem_pool->BlkIx; i < pmem_pool->BlkNbr; i++) {        /* Find ix of mem blk.                              */
;;;2074           p_addr = pmem_pool->PoolPtrs[i];
;;;2075           if (p_addr == pmem_blk) {
;;;2076               addr_valid = DEF_YES;
;;;2077               break;
;;;2078           }
;;;2079       }
;;;2080                                                                       /* Return ix of mem blk in tbl.                     */
;;;2081       if (addr_valid == DEF_YES) {
;;;2082           pool_ix = pmem_pool->BlkNbr - 1 - i;
;;;2083           CPU_CRITICAL_EXIT();
;;;2084          *perr = LIB_MEM_ERR_NONE;
;;;2085           return (pool_ix);
;;;2086       } else {
;;;2087           CPU_CRITICAL_EXIT();
;;;2088          *perr = LIB_MEM_ERR_INVALID_POOL;
;;;2089           return (invalid_ix);
;;;2090       }
;;;2091   
;;;2092   }
00003c  e8bd87f0          POP      {r4-r10,pc}
                  |L12.64|
000040  8020              STRH     r0,[r4,#0]            ;2031
000042  4648              MOV      r0,r9                 ;2032
000044  e7fa              B        |L12.60|
                  |L12.70|
000046  8020              STRH     r0,[r4,#0]            ;2036
000048  4648              MOV      r0,r9                 ;2037
00004a  e7f7              B        |L12.60|
                  |L12.76|
00004c  4631              MOV      r1,r6                 ;2050
00004e  4628              MOV      r0,r5                 ;2050
000050  f7fffffe          BL       Mem_PoolBlkIsValidAddr
000054  2801              CMP      r0,#1                 ;2051
000056  d007              BEQ      |L12.104|
000058  4638              MOV      r0,r7                 ;2052
00005a  f7fffffe          BL       CPU_SR_Restore
00005e  f2427097          MOV      r0,#0x2797            ;2053
000062  8020              STRH     r0,[r4,#0]            ;2053
000064  4648              MOV      r0,r9                 ;2054
000066  e7e9              B        |L12.60|
                  |L12.104|
000068  2200              MOVS     r2,#0                 ;2057
00006a  6a6b              LDR      r3,[r5,#0x24]         ;2057
00006c  e00d              B        |L12.138|
                  |L12.110|
00006e  6a28              LDR      r0,[r5,#0x20]         ;2058
000070  f8500022          LDR      r0,[r0,r2,LSL #2]     ;2058
000074  42b0              CMP      r0,r6                 ;2058
000076  d107              BNE      |L12.136|
000078  4638              MOV      r0,r7                 ;2059
00007a  f7fffffe          BL       CPU_SR_Restore
00007e  f2427098          MOV      r0,#0x2798            ;2060
000082  8020              STRH     r0,[r4,#0]            ;2060
000084  4648              MOV      r0,r9                 ;2061
000086  e7d9              B        |L12.60|
                  |L12.136|
000088  1c52              ADDS     r2,r2,#1              ;2057
                  |L12.138|
00008a  4293              CMP      r3,r2                 ;2057
00008c  d8ef              BHI      |L12.110|
00008e  6ae8              LDR      r0,[r5,#0x2c]         ;2066
000090  4283              CMP      r3,r0                 ;2066
000092  d307              BCC      |L12.164|
000094  4638              MOV      r0,r7                 ;2067
000096  f7fffffe          BL       CPU_SR_Restore
00009a  f24270dd          MOV      r0,#0x27dd            ;2068
00009e  8020              STRH     r0,[r4,#0]            ;2068
0000a0  4648              MOV      r0,r9                 ;2069
0000a2  e7cb              B        |L12.60|
                  |L12.164|
0000a4  2200              MOVS     r2,#0                 ;2072
0000a6  e007              B        |L12.184|
                  |L12.168|
0000a8  6a29              LDR      r1,[r5,#0x20]         ;2074
0000aa  f8511023          LDR      r1,[r1,r3,LSL #2]     ;2074
0000ae  42b1              CMP      r1,r6                 ;2075
0000b0  d101              BNE      |L12.182|
0000b2  2201              MOVS     r2,#1                 ;2076
0000b4  e002              B        |L12.188|
                  |L12.182|
0000b6  1c5b              ADDS     r3,r3,#1              ;2073
                  |L12.184|
0000b8  4298              CMP      r0,r3                 ;2073
0000ba  d8f5              BHI      |L12.168|
                  |L12.188|
0000bc  2a01              CMP      r2,#1                 ;2081
0000be  d006              BEQ      |L12.206|
0000c0  4638              MOV      r0,r7                 ;2087
0000c2  f7fffffe          BL       CPU_SR_Restore
0000c6  f8a48000          STRH     r8,[r4,#0]            ;2088
0000ca  4648              MOV      r0,r9                 ;2089
0000cc  e7b6              B        |L12.60|
                  |L12.206|
0000ce  1ac5              SUBS     r5,r0,r3              ;2082
0000d0  1e6d              SUBS     r5,r5,#1              ;2082
0000d2  4638              MOV      r0,r7                 ;2083
0000d4  f7fffffe          BL       CPU_SR_Restore
0000d8  f2427010          MOV      r0,#0x2710            ;2084
0000dc  8020              STRH     r0,[r4,#0]            ;2084
0000de  4628              MOV      r0,r5                 ;2085
0000e0  e7ac              B        |L12.60|
;;;2093   #endif
                          ENDP

0000e2  0000              DCW      0x0000
                  |L12.228|
                          DCD      0x4c4f4f50

                          AREA ||i.Mem_PoolClr||, CODE, READONLY, ALIGN=2

                  Mem_PoolClr PROC
;;;1014   #if (LIB_MEM_CFG_ALLOC_EN == DEF_ENABLED)
;;;1015   void  Mem_PoolClr (MEM_POOL  *pmem_pool,
000000  b570              PUSH     {r4-r6,lr}
;;;1016                      LIB_ERR   *perr)
;;;1017   {
000002  4604              MOV      r4,r0
000004  460d              MOV      r5,r1
;;;1018   
;;;1019   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)                 /* -------------- VALIDATE RTN ERR  PTR --------------- */
;;;1020       if (perr == (LIB_ERR *)0) {
000006  2d00              CMP      r5,#0
000008  d101              BNE      |L13.14|
;;;1021           CPU_SW_EXCEPTION(;);
00000a  f7fffffe          BL       CPU_SW_Exception
                  |L13.14|
;;;1022       }
;;;1023   #endif
;;;1024   
;;;1025                                                                   /* -------------- VALIDATE MEM POOL PTR --------------- */
;;;1026       if (pmem_pool == (MEM_POOL *)0) {
00000e  b1bc              CBZ      r4,|L13.64|
;;;1027          *perr = LIB_MEM_ERR_NULL_PTR;
;;;1028           return;
;;;1029       }
;;;1030   
;;;1031   
;;;1032       pmem_pool->Type             = (LIB_MEM_TYPE)LIB_MEM_TYPE_NONE;
000010  480d              LDR      r0,|L13.72|
000012  6020              STR      r0,[r4,#0]
;;;1033       pmem_pool->SegHeadPtr       = (MEM_POOL   *)0;
000014  2000              MOVS     r0,#0
000016  6060              STR      r0,[r4,#4]
;;;1034       pmem_pool->SegPrevPtr       = (MEM_POOL   *)0;
000018  60a0              STR      r0,[r4,#8]
;;;1035       pmem_pool->SegNextPtr       = (MEM_POOL   *)0;
00001a  60e0              STR      r0,[r4,#0xc]
;;;1036       pmem_pool->PoolPrevPtr      = (MEM_POOL   *)0;
00001c  6120              STR      r0,[r4,#0x10]
;;;1037       pmem_pool->PoolNextPtr      = (MEM_POOL   *)0;
00001e  6160              STR      r0,[r4,#0x14]
;;;1038       pmem_pool->PoolAddrStart    = (void       *)0;
000020  61a0              STR      r0,[r4,#0x18]
;;;1039       pmem_pool->PoolAddrEnd      = (void       *)0;
000022  61e0              STR      r0,[r4,#0x1c]
;;;1040       pmem_pool->PoolPtrs         = (void      **)0;
000024  6220              STR      r0,[r4,#0x20]
;;;1041       pmem_pool->PoolSize         = (CPU_SIZE_T  )0u;
000026  62a0              STR      r0,[r4,#0x28]
;;;1042       pmem_pool->BlkAlign         = (CPU_SIZE_T  )0u;
000028  6360              STR      r0,[r4,#0x34]
;;;1043       pmem_pool->BlkSize          = (CPU_SIZE_T  )0u;
00002a  6320              STR      r0,[r4,#0x30]
;;;1044       pmem_pool->BlkNbr           = (CPU_SIZE_T  )0u;
00002c  62e0              STR      r0,[r4,#0x2c]
;;;1045       pmem_pool->BlkIx            = (MEM_POOL_IX )0u;
00002e  6260              STR      r0,[r4,#0x24]
;;;1046       pmem_pool->SegAddr          = (void       *)0;
000030  63a0              STR      r0,[r4,#0x38]
;;;1047       pmem_pool->SegAddrNextAvail = (void       *)0;
000032  63e0              STR      r0,[r4,#0x3c]
;;;1048       pmem_pool->SegSizeTot       = (CPU_SIZE_T  )0u;
000034  6420              STR      r0,[r4,#0x40]
;;;1049       pmem_pool->SegSizeRem       = (CPU_SIZE_T  )0u;
000036  6460              STR      r0,[r4,#0x44]
;;;1050   
;;;1051   
;;;1052      *perr = LIB_MEM_ERR_NONE;
000038  f2427010          MOV      r0,#0x2710
00003c  8028              STRH     r0,[r5,#0]
;;;1053   }
00003e  bd70              POP      {r4-r6,pc}
                  |L13.64|
000040  f2427011          MOV      r0,#0x2711            ;1027
000044  8028              STRH     r0,[r5,#0]            ;1027
000046  bd70              POP      {r4-r6,pc}
;;;1054   #endif
                          ENDP

                  |L13.72|
                          DCD      0x454e4f4e

                          AREA ||i.Mem_PoolCreate||, CODE, READONLY, ALIGN=2

                  Mem_PoolCreate PROC
;;;1209   #if (LIB_MEM_CFG_ALLOC_EN == DEF_ENABLED)
;;;1210   void  Mem_PoolCreate (MEM_POOL          *pmem_pool,
000000  e92d4fff          PUSH     {r0-r11,lr}
;;;1211                         void              *pmem_base_addr,
;;;1212                         CPU_SIZE_T         mem_size,
;;;1213                         MEM_POOL_BLK_QTY   blk_nbr,
;;;1214                         CPU_SIZE_T         blk_size,
;;;1215                         CPU_SIZE_T         blk_align,
;;;1216                         CPU_SIZE_T        *poctets_reqd,
;;;1217                         LIB_ERR           *perr)
;;;1218   {
000004  b089              SUB      sp,sp,#0x24
000006  4604              MOV      r4,r0
000008  e9dd8618          LDRD     r8,r6,[sp,#0x60]
00000c  468a              MOV      r10,r1
00000e  4691              MOV      r9,r2
;;;1219       MEM_POOL           *pmem_pool_heap;
;;;1220       MEM_POOL           *pmem_pool_next;
;;;1221       MEM_POOL           *pmem_seg;
;;;1222       MEM_POOL           *pmem_seg_prev;
;;;1223       MEM_POOL           *pmem_seg_next;
;;;1224       void              **ppool_ptr;
;;;1225       void               *pmem_blk;
;;;1226       CPU_INT08U         *pmem_addr_ptrs;
;;;1227       CPU_INT08U         *pmem_addr_pool;
;;;1228       CPU_INT08U         *pmem_base_addr_start;
;;;1229       CPU_INT08U         *pmem_base_addr_end;
;;;1230       CPU_INT08U         *pmem_seg_addr_start;
;;;1231       CPU_INT08U         *pmem_seg_addr_end;
;;;1232       MEM_POOL_BLK_QTY    blk_rem;
;;;1233       CPU_SIZE_T          octets_reqd_unused;
;;;1234       CPU_SIZE_T          size_tot;
;;;1235       CPU_SIZE_T          size_tot_ptrs;
;;;1236       CPU_SIZE_T          size_tot_pool;
;;;1237       CPU_SIZE_T          size_rem;
;;;1238       CPU_SIZE_T          size_pool_ptrs;
;;;1239       CPU_SIZE_T          i;
;;;1240       CPU_SR_ALLOC();
;;;1241   
;;;1242   
;;;1243   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)                     /* ------------- VALIDATE RTN ERR PTR ------------- */
;;;1244       if (perr == (LIB_ERR *)0) {
000010  2e00              CMP      r6,#0
000012  d101              BNE      |L14.24|
;;;1245           CPU_SW_EXCEPTION(;);
000014  f7fffffe          BL       CPU_SW_Exception
                  |L14.24|
;;;1246       }
;;;1247   #endif
;;;1248   
;;;1249                                                                       /* ------------ VALIDATE RTN OCTETS PTR ----------- */
;;;1250       if (poctets_reqd == (CPU_SIZE_T *) 0) {                         /* If NOT avail, ...                                */
000018  f1b80f00          CMP      r8,#0
00001c  d101              BNE      |L14.34|
;;;1251           poctets_reqd  = (CPU_SIZE_T *)&octets_reqd_unused;          /* ... re-cfg NULL rtn ptr to unused local var.     */
00001e  f10d0814          ADD      r8,sp,#0x14
                  |L14.34|
;;;1252          (void)&octets_reqd_unused;                                   /* Prevent possible 'variable unused' warning.      */
;;;1253       }
;;;1254      *poctets_reqd = 0u;                                              /* Init octets req'd for err (see Note #4).         */
000022  2000              MOVS     r0,#0
000024  f8c80000          STR      r0,[r8,#0]
;;;1255   
;;;1256   
;;;1257   
;;;1258       Mem_PoolClr(pmem_pool, perr);                                   /* Init mem pool     for err (see Note #4).         */
000028  4631              MOV      r1,r6
00002a  4620              MOV      r0,r4
00002c  f7fffffe          BL       Mem_PoolClr
;;;1259       if (*perr != LIB_MEM_ERR_NONE) {
000030  8831              LDRH     r1,[r6,#0]
000032  f5a1501c          SUB      r0,r1,#0x2700
000036  3810              SUBS     r0,r0,#0x10
000038  d123              BNE      |L14.130|
;;;1260            return;
;;;1261       }
;;;1262   
;;;1263   
;;;1264                                                                       /* ----------- VALIDATE MEM POOL CREATE ----------- */
;;;1265   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;1266       if (pmem_base_addr != (void *)0) {
00003a  f1ba0f00          CMP      r10,#0
00003e  d002              BEQ      |L14.70|
;;;1267           if (mem_size < 1) {
000040  f1b90f00          CMP      r9,#0
000044  d020              BEQ      |L14.136|
                  |L14.70|
;;;1268              *perr = LIB_MEM_ERR_INVALID_SEG_SIZE;
;;;1269               return;
;;;1270           }
;;;1271       }
;;;1272   
;;;1273       if (blk_nbr < 1) {
000046  980c              LDR      r0,[sp,#0x30]
000048  b310              CBZ      r0,|L14.144|
;;;1274          *perr = LIB_MEM_ERR_INVALID_BLK_NBR;
;;;1275           return;
;;;1276       }
;;;1277   
;;;1278       if (blk_size < 1) {
00004a  9816              LDR      r0,[sp,#0x58]
00004c  b320              CBZ      r0,|L14.152|
;;;1279          *perr = LIB_MEM_ERR_INVALID_BLK_SIZE;
;;;1280           return;
;;;1281       }
;;;1282   
;;;1283       if (blk_align < 1) {
00004e  9817              LDR      r0,[sp,#0x5c]
000050  b330              CBZ      r0,|L14.160|
;;;1284          *perr = LIB_MEM_ERR_INVALID_BLK_ALIGN;
;;;1285           return;
;;;1286       }
;;;1287   #endif
;;;1288   
;;;1289   
;;;1290                                                                       /* ------------ VALIDATE MEM POOL TBL ------------- */
;;;1291       if (Mem_PoolTbl == (MEM_POOL *)0) {
000052  48be              LDR      r0,|L14.844|
000054  6800              LDR      r0,[r0,#0]  ; Mem_PoolTbl
000056  b338              CBZ      r0,|L14.168|
;;;1292          *perr = LIB_MEM_ERR_HEAP_NOT_FOUND;
;;;1293           return;
;;;1294       }
;;;1295   
;;;1296   
;;;1297   
;;;1298   /*$PAGE*/
;;;1299                                                                       /* ---------------- CREATE MEM POOL --------------- */
;;;1300       pmem_pool_heap = (MEM_POOL *)&Mem_PoolHeap;
000058  f8dfb2f4          LDR      r11,|L14.848|
;;;1301       size_tot       = (CPU_SIZE_T) 0u;
00005c  2000              MOVS     r0,#0
00005e  9004              STR      r0,[sp,#0x10]
;;;1302   
;;;1303       CPU_CRITICAL_ENTER();
000060  f7fffffe          BL       CPU_SR_Save
000064  9000              STR      r0,[sp,#0]
;;;1304   
;;;1305       if (pmem_base_addr == (void *)0) {                              /* If no base addr, cfg mem pool from heap.         */
000066  f1ba0f00          CMP      r10,#0
00006a  d021              BEQ      |L14.176|
;;;1306           pmem_seg        =  pmem_pool_heap;
;;;1307           pmem_seg_prev   =  pmem_pool_heap;
;;;1308           pmem_seg_next   =  pmem_pool_heap;
;;;1309   
;;;1310                                                                       /* --------------- VALIDATE MEM SEG --------------- */
;;;1311                                                                       /* Calc tot mem   size for mem pool ptrs.           */
;;;1312           pmem_addr_ptrs  = (CPU_INT08U *)pmem_pool_heap->SegAddrNextAvail;
;;;1313           size_tot_ptrs   =  Mem_SegCalcTotSize((void     *)pmem_addr_ptrs,
;;;1314                                                 (CPU_SIZE_T)blk_nbr,
;;;1315                                                 (CPU_SIZE_T)sizeof(void *),
;;;1316                                                 (CPU_SIZE_T)sizeof(void *));
;;;1317   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;1318           if (size_tot_ptrs < 1) {                                    /* If heap ovf, ...                                 */
;;;1319               CPU_CRITICAL_EXIT();
;;;1320              *perr = LIB_MEM_ERR_HEAP_OVF;                            /* ... rtn err but add'l heap size NOT avail.       */
;;;1321               return;
;;;1322           }
;;;1323   #endif
;;;1324                                                                       /* Calc tot mem   size for mem blks.                */
;;;1325           pmem_addr_pool  =  pmem_addr_ptrs + size_tot_ptrs;          /* Adj next avail addr for mem pool blks.           */
;;;1326           size_tot_pool   =  Mem_SegCalcTotSize((void     *)pmem_addr_pool,
;;;1327                                                 (CPU_SIZE_T)blk_nbr,
;;;1328                                                 (CPU_SIZE_T)blk_size,
;;;1329                                                 (CPU_SIZE_T)blk_align);
;;;1330   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;1331           if (size_tot_pool < 1) {                                    /* If heap ovf, ...                                 */
;;;1332               CPU_CRITICAL_EXIT();
;;;1333              *perr = LIB_MEM_ERR_HEAP_OVF;                            /* ... rtn err but add'l heap size NOT avail.       */
;;;1334               return;
;;;1335           }
;;;1336   #endif
;;;1337   
;;;1338           size_tot = size_tot_ptrs + size_tot_pool;
;;;1339   
;;;1340   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;1341           if ((size_tot < size_tot_ptrs) ||                           /* If heap ovf, ...                                 */
;;;1342               (size_tot < size_tot_pool)) {
;;;1343               CPU_CRITICAL_EXIT();
;;;1344              *perr = LIB_MEM_ERR_HEAP_OVF;                            /* ... rtn err but add'l heap size NOT avail.       */
;;;1345               return;
;;;1346           }
;;;1347   #endif
;;;1348   
;;;1349           size_rem = pmem_pool_heap->SegSizeRem;
;;;1350           if (size_tot > size_rem) {                                  /* If tot size > rem  size, ...                     */
;;;1351               CPU_CRITICAL_EXIT();
;;;1352              *poctets_reqd = size_tot - size_rem;                     /* ... rtn add'l heap size needed.                  */
;;;1353              *perr         = LIB_MEM_ERR_HEAP_EMPTY;
;;;1354               return;
;;;1355           }
;;;1356   
;;;1357   /*$PAGE*/
;;;1358       } else {                                                        /* Else cfg mem pool from dedicated mem.            */
;;;1359                                                                       /* -------- SRCH ALL MEM SEGS FOR MEM POOL -------- */
;;;1360           pmem_base_addr_start = (CPU_INT08U *)pmem_base_addr;
;;;1361           pmem_base_addr_end   = (CPU_INT08U *)pmem_base_addr + mem_size - 1;
00006c  eb0a0009          ADD      r0,r10,r9
000070  1e40              SUBS     r0,r0,#1
;;;1362   
;;;1363   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;1364           if (pmem_base_addr_end < pmem_base_addr_start) {            /* Chk ovf of end addr.                             */
000072  4550              CMP      r0,r10
000074  d26a              BCS      |L14.332|
;;;1365               CPU_CRITICAL_EXIT();
000076  9800              LDR      r0,[sp,#0]
000078  f7fffffe          BL       CPU_SR_Restore
;;;1366              *perr = LIB_MEM_ERR_INVALID_BLK_ADDR;
00007c  f2427097          MOV      r0,#0x2797
000080  8030              STRH     r0,[r6,#0]
                  |L14.130|
;;;1367               return;
;;;1368           }
;;;1369   #endif
;;;1370   
;;;1371           pmem_seg      = (MEM_POOL *)0;
;;;1372           pmem_seg_prev = (MEM_POOL *)0;
;;;1373           pmem_seg_next =  Mem_PoolTbl;
;;;1374   
;;;1375           while (pmem_seg_next != (MEM_POOL *)0) {                    /* Srch tbl for mem seg with same base addr/size.   */
;;;1376   
;;;1377               if ((pmem_base_addr == pmem_seg_next->SegAddr) &&       /* If same base addr/size found, ...                */
;;;1378                   (mem_size       == pmem_seg_next->SegSizeTot)) {
;;;1379   
;;;1380                    pmem_seg        = pmem_seg_next;                   /* ... mem seg already avail in tbl.                */
;;;1381                    break;
;;;1382   
;;;1383               } else {
;;;1384                   pmem_seg_addr_start = (CPU_INT08U *)pmem_seg_next->SegAddr;
;;;1385                   pmem_seg_addr_end   = (CPU_INT08U *)pmem_seg_next->SegAddr + pmem_seg_next->SegSizeTot - 1;
;;;1386   
;;;1387   
;;;1388                   if (pmem_base_addr_end < pmem_seg_addr_start) {     /* If mem seg addr/size prior to next mem seg, ...  */
;;;1389                       break;                                          /* ... new mem seg NOT avail in tbl.                */
;;;1390   
;;;1391                                                                       /* If mem seg overlaps prev mem seg(s) in tbl, ...  */
;;;1392                   } else if (((pmem_base_addr_start <= pmem_seg_addr_start)  &&
;;;1393                               (pmem_base_addr_end   >= pmem_seg_addr_start)) ||
;;;1394                              ((pmem_base_addr_start >= pmem_seg_addr_start)  &&
;;;1395                               (pmem_base_addr_end   <= pmem_seg_addr_end  )) ||
;;;1396                              ((pmem_base_addr_start <= pmem_seg_addr_end  )  &&
;;;1397                               (pmem_base_addr_end   >= pmem_seg_addr_end  ))) {
;;;1398                       CPU_CRITICAL_EXIT();
;;;1399                      *perr = LIB_MEM_ERR_INVALID_SEG_OVERLAP;         /* ... rtn err.                                     */
;;;1400                       return;
;;;1401                   }
;;;1402               }
;;;1403                                                                       /* If mem seg NOT found, adv to next mem seg.       */
;;;1404               pmem_seg_prev = pmem_seg_next;
;;;1405               pmem_seg_next = pmem_seg_next->SegNextPtr;
;;;1406           }
;;;1407   
;;;1408           if (pmem_seg == (MEM_POOL *)0) {                            /* If mem seg NOT found, add    new  mem seg.       */
;;;1409               pmem_seg                    = pmem_pool;
;;;1410               pmem_pool->SegAddr          = pmem_base_addr;
;;;1411               pmem_pool->SegAddrNextAvail = pmem_base_addr;
;;;1412               pmem_pool->SegSizeTot       = mem_size;
;;;1413               pmem_pool->SegSizeRem       = mem_size;
;;;1414           }
;;;1415   
;;;1416   /*$PAGE*/
;;;1417                                                                       /* --------------- VALIDATE MEM SEG --------------- */
;;;1418                                                                       /* Calc tot mem size for mem pool ptrs.             */
;;;1419           pmem_addr_ptrs = (CPU_INT08U *)pmem_pool_heap->SegAddrNextAvail;
;;;1420           size_tot_ptrs  =  Mem_SegCalcTotSize((void     *)pmem_addr_ptrs,
;;;1421                                                (CPU_SIZE_T)blk_nbr,
;;;1422                                                (CPU_SIZE_T)sizeof(void *),
;;;1423                                                (CPU_SIZE_T)sizeof(void *));
;;;1424   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;1425           if (size_tot_ptrs < 1) {                                    /* If heap ovf, ...                                 */
;;;1426               CPU_CRITICAL_EXIT();
;;;1427              *perr = LIB_MEM_ERR_HEAP_OVF;                            /* ... rtn err but add'l heap size NOT avail.       */
;;;1428               return;
;;;1429           }
;;;1430   #endif
;;;1431   
;;;1432           size_rem = pmem_pool_heap->SegSizeRem;
;;;1433           if (size_tot_ptrs > size_rem) {                             /* If ptr size > rem  size, ...                     */
;;;1434               CPU_CRITICAL_EXIT();
;;;1435              *poctets_reqd = size_tot_ptrs - size_rem;                /* ... rtn add'l heap size needed.                  */
;;;1436              *perr         = LIB_MEM_ERR_HEAP_EMPTY;
;;;1437               return;
;;;1438           }
;;;1439   
;;;1440                                                                       /* Calc tot mem size for mem blks.                  */
;;;1441           pmem_addr_pool = (CPU_INT08U *)pmem_seg->SegAddrNextAvail;
;;;1442           size_tot_pool  =  Mem_SegCalcTotSize((void     *)pmem_addr_pool,
;;;1443                                                (CPU_SIZE_T)blk_nbr,
;;;1444                                                (CPU_SIZE_T)blk_size,
;;;1445                                                (CPU_SIZE_T)blk_align);
;;;1446   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;1447           if (size_tot_pool < 1) {                                    /* If seg  ovf, ...                                 */
;;;1448               CPU_CRITICAL_EXIT();
;;;1449              *perr = LIB_MEM_ERR_SEG_OVF;                             /* ... rtn err but add'l seg  size NOT avail.       */
;;;1450               return;
;;;1451           }
;;;1452   #endif
;;;1453   
;;;1454           size_rem = pmem_seg->SegSizeRem;
;;;1455           if (size_tot_pool > size_rem) {                             /* If tot size > rem  size, ...                     */
;;;1456               CPU_CRITICAL_EXIT();
;;;1457              *poctets_reqd = size_tot_pool - size_rem;                /* ... rtn add'l seg  size needed.                  */
;;;1458              *perr         = LIB_MEM_ERR_SEG_EMPTY;
;;;1459               return;
;;;1460           }
;;;1461       }
;;;1462   
;;;1463   
;;;1464   /*$PAGE*/
;;;1465                                                                       /* ---------------- ALLOC MEM BLKs ---------------- */
;;;1466       size_pool_ptrs = (CPU_SIZE_T)(blk_nbr * sizeof(void *));
;;;1467                                                                       /* Alloc stk of ptrs for mem blks from heap.        */
;;;1468       ppool_ptr      = (void **)Mem_SegAlloc((MEM_POOL *)pmem_pool_heap,
;;;1469                                              (CPU_SIZE_T)size_pool_ptrs,
;;;1470                                              (CPU_SIZE_T)sizeof(void *));
;;;1471       if (ppool_ptr == (void **)0) {                                  /* If mem pool ptrs alloc failed, ...               */
;;;1472           size_rem = pmem_pool_heap->SegSizeRem;
;;;1473           CPU_CRITICAL_EXIT();
;;;1474                                                                       /* ... rtn add'l heap size needed.                  */
;;;1475           if (pmem_base_addr == (void *)0) {
;;;1476               if (size_tot > size_rem) {
;;;1477                  *poctets_reqd = size_tot - size_rem;
;;;1478               } else {
;;;1479                  *poctets_reqd = size_tot;
;;;1480               }
;;;1481           } else {
;;;1482               if (size_pool_ptrs > size_rem) {
;;;1483                  *poctets_reqd = size_pool_ptrs - size_rem;
;;;1484               } else {
;;;1485                  *poctets_reqd = size_pool_ptrs;
;;;1486               }
;;;1487           }
;;;1488          *perr = LIB_MEM_ERR_HEAP_EMPTY;
;;;1489           return;
;;;1490       }
;;;1491   
;;;1492       for (i = 0u; i < (CPU_SIZE_T)blk_nbr; i++) {                    /* Alloc mem blks from mem seg.                     */
;;;1493           pmem_blk = (void *)Mem_SegAlloc(pmem_seg, blk_size, blk_align);
;;;1494           if (pmem_blk == (void *)0) {                                /* If    mem blks alloc failed, ...                 */
;;;1495               pmem_addr_pool = (CPU_INT08U *)pmem_seg->SegAddrNextAvail;
;;;1496               size_rem       = (CPU_SIZE_T  )pmem_seg->SegSizeRem;
;;;1497               CPU_CRITICAL_EXIT();
;;;1498               blk_rem        =  blk_nbr - (MEM_POOL_BLK_QTY)i;
;;;1499               size_tot       =  Mem_SegCalcTotSize((void           *)pmem_addr_pool,
;;;1500                                                    (MEM_POOL_BLK_QTY)blk_rem,
;;;1501                                                    (CPU_SIZE_T      )blk_size,
;;;1502                                                    (CPU_SIZE_T      )blk_align);
;;;1503                                                                       /* ... rtn add'l seg  size needed.                  */
;;;1504               if (size_tot > size_rem) {
;;;1505                  *poctets_reqd = size_tot - size_rem;
;;;1506               } else {
;;;1507                  *poctets_reqd = size_tot;
;;;1508               }
;;;1509              *perr = LIB_MEM_ERR_SEG_EMPTY;
;;;1510               return;
;;;1511           }
;;;1512           ppool_ptr[i] = pmem_blk;
;;;1513       }
;;;1514   
;;;1515   
;;;1516   /*$PAGE*/
;;;1517                                                                       /* ------------- UPDATE MEM POOL TBL -------------- */
;;;1518       if (pmem_seg == pmem_pool) {                                    /* Add mem pool as new  mem pool tbl seg.           */
;;;1519                                                                       /* Update cur  mem seg  links.                      */
;;;1520           pmem_pool->SegPrevPtr = pmem_seg_prev;
;;;1521           pmem_pool->SegNextPtr = pmem_seg_next;
;;;1522   
;;;1523           if (pmem_seg_prev != (MEM_POOL *)0) {                       /* Update prev mem seg  link.                       */
;;;1524               pmem_seg_prev->SegNextPtr = pmem_pool;
;;;1525           } else {
;;;1526               Mem_PoolTbl               = pmem_pool;                  /* Update      mem tbl.                             */
;;;1527           }
;;;1528   
;;;1529           if (pmem_seg_next != (MEM_POOL *)0) {                       /* Update next mem seg  link.                       */
;;;1530               pmem_seg_next->SegPrevPtr = pmem_pool;
;;;1531           }
;;;1532   
;;;1533       } else {                                                        /* Add mem pool into mem seg.                       */
;;;1534                                                                       /* Update cur  mem pool links.                      */
;;;1535           pmem_pool_next         = pmem_seg->PoolNextPtr;
;;;1536           pmem_pool->PoolPrevPtr = pmem_seg;
;;;1537           pmem_pool->PoolNextPtr = pmem_pool_next;
;;;1538   
;;;1539           pmem_seg->PoolNextPtr  = pmem_pool;                         /* Update prev mem pool link.                       */
;;;1540   
;;;1541           if (pmem_pool_next != (MEM_POOL *)0) {                      /* Update next mem pool link.                       */
;;;1542               pmem_pool_next->PoolPrevPtr = pmem_pool;
;;;1543           }
;;;1544       }
;;;1545   
;;;1546   
;;;1547   
;;;1548                                                                       /* ----------------- CFG MEM POOL ----------------- */
;;;1549       pmem_pool->Type          = (LIB_MEM_TYPE    ) LIB_MEM_TYPE_POOL;
;;;1550       pmem_pool->SegHeadPtr    = (MEM_POOL       *) pmem_seg;
;;;1551       pmem_pool->PoolAddrStart = (void           *) pmem_addr_pool;
;;;1552       pmem_pool->PoolAddrEnd   = (void           *)(pmem_addr_pool + size_tot_pool - 1);
;;;1553       pmem_pool->PoolPtrs      = (void          **) ppool_ptr;
;;;1554       pmem_pool->PoolSize      = (CPU_SIZE_T      ) size_tot_pool;
;;;1555       pmem_pool->BlkAlign      = (CPU_SIZE_T      ) blk_align;
;;;1556       pmem_pool->BlkSize       = (CPU_SIZE_T      ) blk_size;
;;;1557       pmem_pool->BlkNbr        = (MEM_POOL_BLK_QTY) blk_nbr;
;;;1558       pmem_pool->BlkIx         = (MEM_POOL_IX     ) blk_nbr;
;;;1559   
;;;1560   
;;;1561       CPU_CRITICAL_EXIT();
;;;1562   
;;;1563      *perr = LIB_MEM_ERR_NONE;
;;;1564   }
000082  b00d              ADD      sp,sp,#0x34
000084  e8bd8ff0          POP      {r4-r11,pc}
                  |L14.136|
000088  f242707e          MOV      r0,#0x277e            ;1268
00008c  8030              STRH     r0,[r6,#0]            ;1268
00008e  e7f8              B        |L14.130|
                  |L14.144|
000090  f2427092          MOV      r0,#0x2792            ;1274
000094  8030              STRH     r0,[r6,#0]            ;1274
000096  e7f4              B        |L14.130|
                  |L14.152|
000098  f2427093          MOV      r0,#0x2793            ;1279
00009c  8030              STRH     r0,[r6,#0]            ;1279
00009e  e7f0              B        |L14.130|
                  |L14.160|
0000a0  f2427094          MOV      r0,#0x2794            ;1284
0000a4  8030              STRH     r0,[r6,#0]            ;1284
0000a6  e7ec              B        |L14.130|
                  |L14.168|
0000a8  f24270e7          MOV      r0,#0x27e7            ;1292
0000ac  8030              STRH     r0,[r6,#0]            ;1292
0000ae  e7e8              B        |L14.130|
                  |L14.176|
0000b0  f8cdb020          STR      r11,[sp,#0x20]        ;1307
0000b4  465d              MOV      r5,r11                ;1308
0000b6  f8db903c          LDR      r9,[r11,#0x3c]        ;1312
0000ba  465f              MOV      r7,r11                ;1312
0000bc  2304              MOVS     r3,#4                 ;1313
0000be  461a              MOV      r2,r3                 ;1313
0000c0  4648              MOV      r0,r9                 ;1313
0000c2  990c              LDR      r1,[sp,#0x30]         ;1313
0000c4  f7fffffe          BL       Mem_SegCalcTotSize
0000c8  9003              STR      r0,[sp,#0xc]          ;1313
0000ca  9803              LDR      r0,[sp,#0xc]          ;1318
0000cc  b1e8              CBZ      r0,|L14.266|
0000ce  9803              LDR      r0,[sp,#0xc]          ;1325
0000d0  4448              ADD      r0,r0,r9              ;1325
0000d2  9006              STR      r0,[sp,#0x18]         ;1325
0000d4  e9dd2316          LDRD     r2,r3,[sp,#0x58]      ;1326
0000d8  990c              LDR      r1,[sp,#0x30]         ;1326
0000da  9806              LDR      r0,[sp,#0x18]         ;1326
0000dc  f7fffffe          BL       Mem_SegCalcTotSize
0000e0  4681              MOV      r9,r0                 ;1326
0000e2  ea5f0009          MOVS     r0,r9                 ;1331
0000e6  d017              BEQ      |L14.280|
0000e8  9803              LDR      r0,[sp,#0xc]          ;1338
0000ea  4448              ADD      r0,r0,r9              ;1338
0000ec  9004              STR      r0,[sp,#0x10]         ;1338
0000ee  e9dd1003          LDRD     r1,r0,[sp,#0xc]       ;1341
0000f2  4288              CMP      r0,r1                 ;1341
0000f4  d302              BCC      |L14.252|
0000f6  9804              LDR      r0,[sp,#0x10]         ;1342
0000f8  4548              CMP      r0,r9                 ;1342
0000fa  d214              BCS      |L14.294|
                  |L14.252|
0000fc  9800              LDR      r0,[sp,#0]            ;1343
0000fe  f7fffffe          BL       CPU_SR_Restore
000102  f24270e3          MOV      r0,#0x27e3            ;1344
000106  8030              STRH     r0,[r6,#0]            ;1344
000108  e7bb              B        |L14.130|
                  |L14.266|
00010a  9800              LDR      r0,[sp,#0]            ;1319
00010c  f7fffffe          BL       CPU_SR_Restore
000110  f24270e3          MOV      r0,#0x27e3            ;1320
000114  8030              STRH     r0,[r6,#0]            ;1320
000116  e7b4              B        |L14.130|
                  |L14.280|
000118  9800              LDR      r0,[sp,#0]            ;1332
00011a  f7fffffe          BL       CPU_SR_Restore
00011e  f24270e3          MOV      r0,#0x27e3            ;1333
000122  8030              STRH     r0,[r6,#0]            ;1333
000124  e7ad              B        |L14.130|
                  |L14.294|
000126  f8db0044          LDR      r0,[r11,#0x44]        ;1349
00012a  9002              STR      r0,[sp,#8]            ;1349
00012c  9904              LDR      r1,[sp,#0x10]         ;1350
00012e  9802              LDR      r0,[sp,#8]            ;1350
000130  4281              CMP      r1,r0                 ;1350
000132  d97a              BLS      |L14.554|
000134  9800              LDR      r0,[sp,#0]            ;1351
000136  f7fffffe          BL       CPU_SR_Restore
00013a  9902              LDR      r1,[sp,#8]            ;1352
00013c  9804              LDR      r0,[sp,#0x10]         ;1352
00013e  1a40              SUBS     r0,r0,r1              ;1352
000140  f8c80000          STR      r0,[r8,#0]            ;1352
000144  f24270e2          MOV      r0,#0x27e2            ;1353
000148  8030              STRH     r0,[r6,#0]            ;1353
00014a  e79a              B        |L14.130|
                  |L14.332|
00014c  2700              MOVS     r7,#0                 ;1371
00014e  2100              MOVS     r1,#0                 ;1372
000150  9108              STR      r1,[sp,#0x20]         ;1372
000152  497e              LDR      r1,|L14.844|
000154  680d              LDR      r5,[r1,#0]            ;1373  ; Mem_PoolTbl
000156  e01b              B        |L14.400|
                  |L14.344|
000158  6ba9              LDR      r1,[r5,#0x38]         ;1377
00015a  4551              CMP      r1,r10                ;1377
00015c  d104              BNE      |L14.360|
00015e  6c2a              LDR      r2,[r5,#0x40]         ;1378
000160  454a              CMP      r2,r9                 ;1378
000162  d101              BNE      |L14.360|
000164  462f              MOV      r7,r5                 ;1380
000166  e015              B        |L14.404|
                  |L14.360|
000168  6c2a              LDR      r2,[r5,#0x40]         ;1385
00016a  440a              ADD      r2,r2,r1              ;1385
00016c  1e52              SUBS     r2,r2,#1              ;1385
00016e  4288              CMP      r0,r1                 ;1388
000170  d310              BCC      |L14.404|
000172  458a              CMP      r10,r1                ;1392
000174  d903              BLS      |L14.382|
000176  4290              CMP      r0,r2                 ;1395
000178  d901              BLS      |L14.382|
00017a  4592              CMP      r10,r2                ;1396
00017c  d806              BHI      |L14.396|
                  |L14.382|
00017e  9800              LDR      r0,[sp,#0]            ;1398
000180  f7fffffe          BL       CPU_SR_Restore
000184  f242707f          MOV      r0,#0x277f            ;1399
000188  8030              STRH     r0,[r6,#0]            ;1399
00018a  e77a              B        |L14.130|
                  |L14.396|
00018c  9508              STR      r5,[sp,#0x20]         ;1404
00018e  68ed              LDR      r5,[r5,#0xc]          ;1405
                  |L14.400|
000190  2d00              CMP      r5,#0                 ;1375
000192  d1e1              BNE      |L14.344|
                  |L14.404|
000194  b947              CBNZ     r7,|L14.424|
000196  4627              MOV      r7,r4                 ;1409
000198  f8c4a038          STR      r10,[r4,#0x38]        ;1410
00019c  f8c4a03c          STR      r10,[r4,#0x3c]        ;1411
0001a0  f8c49040          STR      r9,[r4,#0x40]         ;1412
0001a4  f8c49044          STR      r9,[r4,#0x44]         ;1413
                  |L14.424|
0001a8  f8db003c          LDR      r0,[r11,#0x3c]        ;1419
0001ac  2304              MOVS     r3,#4                 ;1420
0001ae  461a              MOV      r2,r3                 ;1420
0001b0  990c              LDR      r1,[sp,#0x30]         ;1420
0001b2  f7fffffe          BL       Mem_SegCalcTotSize
0001b6  4681              MOV      r9,r0                 ;1420
0001b8  f1b90f00          CMP      r9,#0                 ;1425
0001bc  d011              BEQ      |L14.482|
0001be  f8db0044          LDR      r0,[r11,#0x44]        ;1432
0001c2  9002              STR      r0,[sp,#8]            ;1432
0001c4  9802              LDR      r0,[sp,#8]            ;1433
0001c6  4581              CMP      r9,r0                 ;1433
0001c8  d912              BLS      |L14.496|
0001ca  9800              LDR      r0,[sp,#0]            ;1434
0001cc  f7fffffe          BL       CPU_SR_Restore
0001d0  9802              LDR      r0,[sp,#8]            ;1435
0001d2  eba90000          SUB      r0,r9,r0              ;1435
0001d6  f8c80000          STR      r0,[r8,#0]            ;1435
0001da  f24270e2          MOV      r0,#0x27e2            ;1436
0001de  8030              STRH     r0,[r6,#0]            ;1436
0001e0  e74f              B        |L14.130|
                  |L14.482|
0001e2  9800              LDR      r0,[sp,#0]            ;1426
0001e4  f7fffffe          BL       CPU_SR_Restore
0001e8  f24270e3          MOV      r0,#0x27e3            ;1427
0001ec  8030              STRH     r0,[r6,#0]            ;1427
0001ee  e748              B        |L14.130|
                  |L14.496|
0001f0  6bf8              LDR      r0,[r7,#0x3c]         ;1441
0001f2  9006              STR      r0,[sp,#0x18]         ;1441
0001f4  e9dd2316          LDRD     r2,r3,[sp,#0x58]      ;1442
0001f8  990c              LDR      r1,[sp,#0x30]         ;1442
0001fa  9806              LDR      r0,[sp,#0x18]         ;1442
0001fc  f7fffffe          BL       Mem_SegCalcTotSize
000200  4681              MOV      r9,r0                 ;1442
000202  ea5f0009          MOVS     r0,r9                 ;1447
000206  d011              BEQ      |L14.556|
000208  6c78              LDR      r0,[r7,#0x44]         ;1454
00020a  9002              STR      r0,[sp,#8]            ;1454
00020c  9802              LDR      r0,[sp,#8]            ;1455
00020e  4581              CMP      r9,r0                 ;1455
000210  d913              BLS      |L14.570|
000212  9800              LDR      r0,[sp,#0]            ;1456
000214  f7fffffe          BL       CPU_SR_Restore
000218  9802              LDR      r0,[sp,#8]            ;1457
00021a  eba90000          SUB      r0,r9,r0              ;1457
00021e  f8c80000          STR      r0,[r8,#0]            ;1457
000222  f24270d8          MOV      r0,#0x27d8            ;1458
000226  8030              STRH     r0,[r6,#0]            ;1458
000228  e72b              B        |L14.130|
                  |L14.554|
00022a  e006              B        |L14.570|
                  |L14.556|
00022c  9800              LDR      r0,[sp,#0]            ;1448
00022e  f7fffffe          BL       CPU_SR_Restore
000232  f24270d9          MOV      r0,#0x27d9            ;1449
000236  8030              STRH     r0,[r6,#0]            ;1449
000238  e723              B        |L14.130|
                  |L14.570|
00023a  980c              LDR      r0,[sp,#0x30]         ;1466
00023c  0080              LSLS     r0,r0,#2              ;1466
00023e  9001              STR      r0,[sp,#4]            ;1466
000240  2204              MOVS     r2,#4                 ;1468
000242  4658              MOV      r0,r11                ;1468
000244  9901              LDR      r1,[sp,#4]            ;1468
000246  f7fffffe          BL       Mem_SegAlloc
00024a  9007              STR      r0,[sp,#0x1c]         ;1468
00024c  9807              LDR      r0,[sp,#0x1c]         ;1471
00024e  b110              CBZ      r0,|L14.598|
000250  f04f0a00          MOV      r10,#0                ;1492
000254  e02d              B        |L14.690|
                  |L14.598|
000256  f8db4044          LDR      r4,[r11,#0x44]        ;1472
00025a  9800              LDR      r0,[sp,#0]            ;1473
00025c  f7fffffe          BL       CPU_SR_Restore
000260  f1ba0f00          CMP      r10,#0                ;1475
000264  d007              BEQ      |L14.630|
000266  9801              LDR      r0,[sp,#4]            ;1482
000268  42a0              CMP      r0,r4                 ;1482
00026a  d910              BLS      |L14.654|
00026c  9801              LDR      r0,[sp,#4]            ;1483
00026e  1b00              SUBS     r0,r0,r4              ;1483
000270  f8c80000          STR      r0,[r8,#0]            ;1483
000274  e00e              B        |L14.660|
                  |L14.630|
000276  9804              LDR      r0,[sp,#0x10]         ;1476
000278  42a0              CMP      r0,r4                 ;1476
00027a  d904              BLS      |L14.646|
00027c  9804              LDR      r0,[sp,#0x10]         ;1477
00027e  1b00              SUBS     r0,r0,r4              ;1477
000280  f8c80000          STR      r0,[r8,#0]            ;1477
000284  e006              B        |L14.660|
                  |L14.646|
000286  9804              LDR      r0,[sp,#0x10]         ;1479
000288  f8c80000          STR      r0,[r8,#0]            ;1479
00028c  e002              B        |L14.660|
                  |L14.654|
00028e  9801              LDR      r0,[sp,#4]            ;1485
000290  f8c80000          STR      r0,[r8,#0]            ;1485
                  |L14.660|
000294  f24270e2          MOV      r0,#0x27e2            ;1488
000298  8030              STRH     r0,[r6,#0]            ;1488
00029a  e6f2              B        |L14.130|
                  |L14.668|
00029c  e9dd1216          LDRD     r1,r2,[sp,#0x58]      ;1493
0002a0  4638              MOV      r0,r7                 ;1493
0002a2  f7fffffe          BL       Mem_SegAlloc
0002a6  b188              CBZ      r0,|L14.716|
0002a8  9907              LDR      r1,[sp,#0x1c]         ;1512
0002aa  f841002a          STR      r0,[r1,r10,LSL #2]    ;1512
0002ae  f10a0a01          ADD      r10,r10,#1            ;1492
                  |L14.690|
0002b2  980c              LDR      r0,[sp,#0x30]         ;1492
0002b4  4582              CMP      r10,r0                ;1492
0002b6  d3f1              BCC      |L14.668|
0002b8  42a7              CMP      r7,r4                 ;1518
0002ba  d125              BNE      |L14.776|
0002bc  9808              LDR      r0,[sp,#0x20]         ;1520
0002be  60a0              STR      r0,[r4,#8]            ;1520
0002c0  60e5              STR      r5,[r4,#0xc]          ;1521
0002c2  9808              LDR      r0,[sp,#0x20]         ;1523
0002c4  b1d8              CBZ      r0,|L14.766|
0002c6  9808              LDR      r0,[sp,#0x20]         ;1524
0002c8  60c4              STR      r4,[r0,#0xc]          ;1524
0002ca  e01a              B        |L14.770|
                  |L14.716|
0002cc  6bfd              LDR      r5,[r7,#0x3c]         ;1495
0002ce  6c7c              LDR      r4,[r7,#0x44]         ;1496
0002d0  9800              LDR      r0,[sp,#0]            ;1497
0002d2  f7fffffe          BL       CPU_SR_Restore
0002d6  980c              LDR      r0,[sp,#0x30]         ;1498
0002d8  eba0010a          SUB      r1,r0,r10             ;1498
0002dc  e9dd2316          LDRD     r2,r3,[sp,#0x58]      ;1499
0002e0  4628              MOV      r0,r5                 ;1499
0002e2  f7fffffe          BL       Mem_SegCalcTotSize
0002e6  42a0              CMP      r0,r4                 ;1504
0002e8  d903              BLS      |L14.754|
0002ea  1b00              SUBS     r0,r0,r4              ;1505
0002ec  f8c80000          STR      r0,[r8,#0]            ;1505
0002f0  e001              B        |L14.758|
                  |L14.754|
0002f2  f8c80000          STR      r0,[r8,#0]            ;1507
                  |L14.758|
0002f6  f24270d8          MOV      r0,#0x27d8            ;1509
0002fa  8030              STRH     r0,[r6,#0]            ;1509
0002fc  e6c1              B        |L14.130|
                  |L14.766|
0002fe  4813              LDR      r0,|L14.844|
000300  6004              STR      r4,[r0,#0]            ;1526  ; Mem_PoolTbl
                  |L14.770|
000302  b13d              CBZ      r5,|L14.788|
000304  60ac              STR      r4,[r5,#8]            ;1530
000306  e005              B        |L14.788|
                  |L14.776|
000308  6978              LDR      r0,[r7,#0x14]         ;1535
00030a  6127              STR      r7,[r4,#0x10]         ;1536
00030c  6160              STR      r0,[r4,#0x14]         ;1537
00030e  617c              STR      r4,[r7,#0x14]         ;1539
000310  b100              CBZ      r0,|L14.788|
000312  6104              STR      r4,[r0,#0x10]         ;1542
                  |L14.788|
000314  480f              LDR      r0,|L14.852|
000316  6020              STR      r0,[r4,#0]            ;1549
000318  6067              STR      r7,[r4,#4]            ;1550
00031a  9806              LDR      r0,[sp,#0x18]         ;1551
00031c  61a0              STR      r0,[r4,#0x18]         ;1551
00031e  9806              LDR      r0,[sp,#0x18]         ;1552
000320  4448              ADD      r0,r0,r9              ;1552
000322  1e40              SUBS     r0,r0,#1              ;1552
000324  61e0              STR      r0,[r4,#0x1c]         ;1552
000326  9807              LDR      r0,[sp,#0x1c]         ;1553
000328  6220              STR      r0,[r4,#0x20]         ;1553
00032a  f8c49028          STR      r9,[r4,#0x28]         ;1554
00032e  9817              LDR      r0,[sp,#0x5c]         ;1555
000330  6360              STR      r0,[r4,#0x34]         ;1555
000332  9816              LDR      r0,[sp,#0x58]         ;1556
000334  6320              STR      r0,[r4,#0x30]         ;1556
000336  980c              LDR      r0,[sp,#0x30]         ;1557
000338  62e0              STR      r0,[r4,#0x2c]         ;1557
00033a  980c              LDR      r0,[sp,#0x30]         ;1558
00033c  6260              STR      r0,[r4,#0x24]         ;1558
00033e  9800              LDR      r0,[sp,#0]            ;1561
000340  f7fffffe          BL       CPU_SR_Restore
000344  f2427010          MOV      r0,#0x2710            ;1563
000348  8030              STRH     r0,[r6,#0]            ;1563
00034a  e69a              B        |L14.130|
;;;1565   #endif
                          ENDP

                  |L14.844|
                          DCD      ||.data||
                  |L14.848|
                          DCD      ||.bss||
                  |L14.852|
                          DCD      0x4c4f4f50

                          AREA ||i.Mem_SegAlloc||, CODE, READONLY, ALIGN=1

                  Mem_SegAlloc PROC
;;;2392   #if (LIB_MEM_CFG_ALLOC_EN == DEF_ENABLED)
;;;2393   static  void  *Mem_SegAlloc (MEM_POOL    *pmem_pool,
000000  b530              PUSH     {r4,r5,lr}
;;;2394                                CPU_SIZE_T   size,
;;;2395                                CPU_SIZE_T   align)
;;;2396   {
;;;2397       CPU_INT08U  *pmem_addr;
;;;2398       CPU_INT08U  *pmem_addr_next;
;;;2399       CPU_SIZE_T   mem_align;
;;;2400       CPU_SIZE_T   align_offset;
;;;2401       CPU_SIZE_T   size_tot;
;;;2402   
;;;2403   
;;;2404       pmem_addr = (CPU_INT08U *)pmem_pool->SegAddrNextAvail;
000002  6bc3              LDR      r3,[r0,#0x3c]
;;;2405   
;;;2406       mem_align = (CPU_SIZE_T)((CPU_ADDR)pmem_addr % align);          /* Calc mem align.                                  */
000004  fbb3f4f2          UDIV     r4,r3,r2
000008  fb023414          MLS      r4,r2,r4,r3
;;;2407   
;;;2408       if (mem_align != 0u) {
00000c  2c00              CMP      r4,#0
00000e  d001              BEQ      |L15.20|
;;;2409           align_offset = align - mem_align;
000010  1b14              SUBS     r4,r2,r4
000012  e000              B        |L15.22|
                  |L15.20|
;;;2410       } else {
;;;2411           align_offset = 0u;
000014  2400              MOVS     r4,#0
                  |L15.22|
;;;2412       }
;;;2413   
;;;2414       size_tot = align_offset + size;
000016  1862              ADDS     r2,r4,r1
;;;2415       if (size_tot > pmem_pool->SegSizeRem) {                         /* If insufficient mem seg size rem, ...            */
000018  6c45              LDR      r5,[r0,#0x44]
00001a  4295              CMP      r5,r2
00001c  d201              BCS      |L15.34|
;;;2416           return ((void *)0);                                         /* ... rtn NULL.                                    */
00001e  2000              MOVS     r0,#0
;;;2417       }
;;;2418   
;;;2419   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;2420       if ((size_tot < align_offset) ||                                /* If size ovf, ...                                 */
;;;2421           (size_tot < size)) {
;;;2422           return ((void *)0);                                         /* ... rtn NULL.                                    */
;;;2423       }
;;;2424   #endif
;;;2425   
;;;2426       pmem_addr_next = pmem_addr + size_tot;
;;;2427   
;;;2428   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;2429       if (pmem_addr_next < pmem_addr) {                               /* If addr ovf, ...                                 */
;;;2430           return ((void *)0);                                         /* ... rtn NULL.                                    */
;;;2431       }
;;;2432   #endif
;;;2433   
;;;2434       pmem_addr += align_offset;                                      /* Align mem addr.                                  */
;;;2435   
;;;2436       pmem_pool->SegAddrNextAvail  = (void     *)pmem_addr_next;      /* Adv next avail addr.                             */
;;;2437       pmem_pool->SegSizeRem       -= (CPU_SIZE_T)size_tot;            /* Adj rem mem seg size.                            */
;;;2438   
;;;2439       return ((void *)pmem_addr);
;;;2440   }
000020  bd30              POP      {r4,r5,pc}
                  |L15.34|
000022  42a2              CMP      r2,r4                 ;2420
000024  d301              BCC      |L15.42|
000026  428a              CMP      r2,r1                 ;2421
000028  d201              BCS      |L15.46|
                  |L15.42|
00002a  2000              MOVS     r0,#0                 ;2422
00002c  bd30              POP      {r4,r5,pc}
                  |L15.46|
00002e  1899              ADDS     r1,r3,r2              ;2426
000030  4299              CMP      r1,r3                 ;2429
000032  d201              BCS      |L15.56|
000034  2000              MOVS     r0,#0                 ;2430
000036  bd30              POP      {r4,r5,pc}
                  |L15.56|
000038  4423              ADD      r3,r3,r4              ;2434
00003a  63c1              STR      r1,[r0,#0x3c]         ;2436
00003c  1aa9              SUBS     r1,r5,r2              ;2437
00003e  6441              STR      r1,[r0,#0x44]         ;2437
000040  4618              MOV      r0,r3                 ;2439
000042  bd30              POP      {r4,r5,pc}
;;;2441   #endif
                          ENDP


                          AREA ||i.Mem_SegCalcTotSize||, CODE, READONLY, ALIGN=1

                  Mem_SegCalcTotSize PROC
;;;2284   #if (LIB_MEM_CFG_ALLOC_EN == DEF_ENABLED)
;;;2285   static  CPU_SIZE_T  Mem_SegCalcTotSize (void              *pmem_addr,
000000  b5f0              PUSH     {r4-r7,lr}
;;;2286                                           MEM_POOL_BLK_QTY   blk_nbr,
;;;2287                                           CPU_SIZE_T         blk_size,
;;;2288                                           CPU_SIZE_T         blk_align)
;;;2289   {
;;;2290   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;2291       CPU_SIZE_T  blk_size_mem_aligned;
;;;2292       CPU_SIZE_T  blk_size_aligned;
;;;2293       CPU_SIZE_T  blk_size_aligned_nbr;
;;;2294       CPU_SIZE_T  blk_size_tot;
;;;2295   #endif
;;;2296       CPU_SIZE_T  align_offset;
;;;2297       CPU_SIZE_T  mem_align_offset;
;;;2298       CPU_SIZE_T  blk_align_offset;
;;;2299       CPU_SIZE_T  size_tot;
;;;2300   
;;;2301                                                                       /* Calc mem align (see Note #2a).                   */
;;;2302       align_offset = (CPU_ADDR)pmem_addr % blk_align;
000002  fbb0f4f3          UDIV     r4,r0,r3
000006  fb030014          MLS      r0,r3,r4,r0
;;;2303       if (align_offset != 0u) {
00000a  2800              CMP      r0,#0
00000c  d001              BEQ      |L16.18|
;;;2304           mem_align_offset = blk_align - align_offset;
00000e  1a1f              SUBS     r7,r3,r0
000010  e000              B        |L16.20|
                  |L16.18|
;;;2305       } else {
;;;2306           mem_align_offset = 0u;
000012  2700              MOVS     r7,#0
                  |L16.20|
;;;2307       }
;;;2308                                                                       /* Calc blk align (see Note #2b).                   */
;;;2309       align_offset = blk_size % blk_align;
000014  fbb2f0f3          UDIV     r0,r2,r3
000018  fb032010          MLS      r0,r3,r0,r2
;;;2310       if (align_offset != 0u) {
00001c  b108              CBZ      r0,|L16.34|
;;;2311           blk_align_offset = blk_align - align_offset;
00001e  1a1d              SUBS     r5,r3,r0
000020  e000              B        |L16.36|
                  |L16.34|
;;;2312       } else {
;;;2313           blk_align_offset = 0u;
000022  2500              MOVS     r5,#0
                  |L16.36|
;;;2314       }
;;;2315                                                                       /* Calc tot size  (see Note #2c).                   */
;;;2316       size_tot = mem_align_offset + ((blk_size + blk_align_offset) * ((CPU_SIZE_T)blk_nbr - 1)) + blk_size;
000024  18be              ADDS     r6,r7,r2
000026  1954              ADDS     r4,r2,r5
000028  1e48              SUBS     r0,r1,#1
00002a  4684              MOV      r12,r0
00002c  fb046000          MLA      r0,r4,r0,r6
;;;2317   
;;;2318   #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)                     /* Chk ovf of tot size = A + [(B + C) * D] + E      */
;;;2319       blk_size_mem_aligned = mem_align_offset + blk_size;             /* Chk ovf of A + E :                               */
;;;2320       if ((blk_size_mem_aligned < mem_align_offset) ||
000030  42be              CMP      r6,r7
000032  d301              BCC      |L16.56|
;;;2321           (blk_size_mem_aligned < blk_size)) {
000034  4296              CMP      r6,r2
000036  d201              BCS      |L16.60|
                  |L16.56|
;;;2322           return (0u);
000038  2000              MOVS     r0,#0
                  |L16.58|
;;;2323       }
;;;2324   
;;;2325       if (blk_nbr > 1) {
;;;2326           blk_size_aligned = blk_size + blk_align_offset;
;;;2327           if ((blk_size_aligned < blk_align_offset) ||                /* Chk ovf of      (B + C) :                        */
;;;2328               (blk_size_aligned < blk_size)) {
;;;2329               return (0u);
;;;2330           }
;;;2331   
;;;2332           blk_size_aligned_nbr = blk_size_aligned * ((CPU_SIZE_T)blk_nbr - 1);
;;;2333           if ((blk_size_aligned_nbr < blk_size_aligned) ||            /* Chk ovf of     [(B + C) * D] :                   */
;;;2334               (blk_size_aligned_nbr < blk_align_offset) ||
;;;2335               (blk_size_aligned_nbr < blk_size)) {
;;;2336               return (0u);
;;;2337           }
;;;2338   
;;;2339           blk_size_tot = blk_size_aligned_nbr + blk_size;
;;;2340           if ((blk_size_tot < blk_size_aligned_nbr) ||                /* Chk ovf of     [(B + C) * D] + E :               */
;;;2341               (blk_size_tot < blk_size)) {
;;;2342               return (0u);
;;;2343           }
;;;2344   
;;;2345           if ((size_tot < blk_size_mem_aligned) ||                    /* Chk ovf of A + [(B + C) * D] + E :               */
;;;2346               (size_tot < blk_size_aligned_nbr) ||
;;;2347               (size_tot < blk_size_tot)) {
;;;2348               return (0u);
;;;2349           }
;;;2350       }
;;;2351   #endif
;;;2352   
;;;2353       return (size_tot);
;;;2354   }
00003a  bdf0              POP      {r4-r7,pc}
                  |L16.60|
00003c  2901              CMP      r1,#1                 ;2325
00003e  d9fc              BLS      |L16.58|
000040  42ac              CMP      r4,r5                 ;2327
000042  d301              BCC      |L16.72|
000044  4294              CMP      r4,r2                 ;2328
000046  d201              BCS      |L16.76|
                  |L16.72|
000048  2000              MOVS     r0,#0                 ;2329
00004a  bdf0              POP      {r4-r7,pc}
                  |L16.76|
00004c  fb04f30c          MUL      r3,r4,r12             ;2332
000050  42a3              CMP      r3,r4                 ;2333
000052  d303              BCC      |L16.92|
000054  42ab              CMP      r3,r5                 ;2334
000056  d301              BCC      |L16.92|
000058  4293              CMP      r3,r2                 ;2335
00005a  d201              BCS      |L16.96|
                  |L16.92|
00005c  2000              MOVS     r0,#0                 ;2336
00005e  bdf0              POP      {r4-r7,pc}
                  |L16.96|
000060  1899              ADDS     r1,r3,r2              ;2339
000062  4299              CMP      r1,r3                 ;2340
000064  d301              BCC      |L16.106|
000066  4291              CMP      r1,r2                 ;2341
000068  d201              BCS      |L16.110|
                  |L16.106|
00006a  2000              MOVS     r0,#0                 ;2342
                  |L16.108|
00006c  bdf0              POP      {r4-r7,pc}
                  |L16.110|
00006e  42b0              CMP      r0,r6                 ;2345
000070  d303              BCC      |L16.122|
000072  4298              CMP      r0,r3                 ;2346
000074  d301              BCC      |L16.122|
000076  4288              CMP      r0,r1                 ;2347
000078  d2f8              BCS      |L16.108|
                  |L16.122|
00007a  2000              MOVS     r0,#0                 ;2348
00007c  bdf0              POP      {r4-r7,pc}
;;;2355   #endif
                          ENDP


                          AREA ||i.Mem_SegGetSizeRem||, CODE, READONLY, ALIGN=2

                  Mem_SegGetSizeRem PROC
;;;909    #if (LIB_MEM_CFG_ALLOC_EN == DEF_ENABLED)
;;;910    CPU_SIZE_T  Mem_SegGetSizeRem (MEM_POOL    *pmem_pool,
000000  e92d41f0          PUSH     {r4-r8,lr}
;;;911                                   CPU_SIZE_T   align,
;;;912                                   LIB_ERR     *perr)
;;;913    {
000004  4606              MOV      r6,r0
000006  460d              MOV      r5,r1
000008  4614              MOV      r4,r2
;;;914        MEM_POOL    *pmem_seg;
;;;915        MEM_POOL    *pmem_seg_size;
;;;916        CPU_SIZE_T   size_rem;
;;;917        CPU_SIZE_T   size_rem_mod;
;;;918        CPU_SIZE_T   seg_addr_mod;
;;;919        CPU_ADDR     seg_addr;
;;;920        CPU_SR_ALLOC();
;;;921    
;;;922    
;;;923    #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;924                                                                    /* --------------- VALIDATE RTN ERR PTR --------------- */
;;;925        if (perr == (LIB_ERR *)0) {
00000a  2c00              CMP      r4,#0
00000c  d101              BNE      |L17.18|
;;;926            CPU_SW_EXCEPTION(0u);
00000e  f7fffffe          BL       CPU_SW_Exception
                  |L17.18|
;;;927        }
;;;928                                                                    /* ---------------- VALIDATE MEM ALIGN ---------------- */
;;;929        if (align < 1) {
;;;930           *perr =  LIB_MEM_ERR_INVALID_MEM_ALIGN;
000012  f2427075          MOV      r0,#0x2775
000016  b135              CBZ      r5,|L17.38|
;;;931            return (0u);
;;;932        }
;;;933    	if (align > DEF_ALIGN_MAX_NBR_OCTETS) {
000018  f5b55f80          CMP      r5,#0x1000
00001c  d906              BLS      |L17.44|
;;;934    	   *perr =  LIB_MEM_ERR_INVALID_MEM_ALIGN;
00001e  8020              STRH     r0,[r4,#0]
;;;935            return (0u);
000020  2000              MOVS     r0,#0
                  |L17.34|
;;;936        }
;;;937                                                                    /* ---------------- VALIDATE MEM POOL ----------------- */
;;;938        if (pmem_pool == (MEM_POOL *)0) {                           /* Validate mem ptr.                                    */
;;;939           *perr =  LIB_MEM_ERR_NULL_PTR;
;;;940            return (0u);
;;;941        }
;;;942    #endif
;;;943    
;;;944        CPU_CRITICAL_ENTER();
;;;945    
;;;946    #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;947        switch (pmem_pool->Type) {                                  /* Validate mem pool type.                              */
;;;948            case LIB_MEM_TYPE_HEAP:
;;;949            case LIB_MEM_TYPE_POOL:
;;;950                 break;
;;;951    
;;;952    
;;;953            case LIB_MEM_TYPE_NONE:
;;;954            default:
;;;955                 CPU_CRITICAL_EXIT();
;;;956                *perr =  LIB_MEM_ERR_INVALID_POOL;
;;;957                 return (0u);                                       /* Prevent 'break NOT reachable' compiler warning.      */
;;;958        }
;;;959    #endif
;;;960    
;;;961                                                                    /* ------------- GET REM'ING MEM SEG SIZE ------------- */
;;;962        pmem_seg      =  pmem_pool->SegHeadPtr;                     /* Get mem pool's head seg.                             */
;;;963        pmem_seg_size = (pmem_seg->SegAddr != (void *)0)
;;;964                      ?  pmem_seg : &Mem_PoolHeap;                  /* See Note #1.                                         */
;;;965        size_rem      =  pmem_seg_size->SegSizeRem;                 /* Get mem seg's rem'ing mem size.                      */
;;;966        seg_addr      = (CPU_ADDR)pmem_seg_size->SegAddrNextAvail;
;;;967    
;;;968        CPU_CRITICAL_EXIT();
;;;969    
;;;970        if (align > 1) {                                            /* If align > 1 octet, ...                              */
;;;971            seg_addr_mod  =  seg_addr % align;
;;;972            size_rem_mod  = (seg_addr_mod > 0u) ? (align - seg_addr_mod) : 0u;
;;;973            size_rem     -=  size_rem_mod;                          /* ... adj rem'ing size by offset to align'd seg addr.  */
;;;974        }
;;;975    
;;;976    
;;;977       *perr =  LIB_MEM_ERR_NONE;
;;;978    
;;;979        return (size_rem);
;;;980    }
000022  e8bd81f0          POP      {r4-r8,pc}
                  |L17.38|
000026  8020              STRH     r0,[r4,#0]            ;930
000028  2000              MOVS     r0,#0                 ;931
00002a  e7fa              B        |L17.34|
                  |L17.44|
00002c  b19e              CBZ      r6,|L17.86|
00002e  f7fffffe          BL       CPU_SR_Save
000032  4a16              LDR      r2,|L17.140|
000034  6831              LDR      r1,[r6,#0]            ;947
000036  1889              ADDS     r1,r1,r2              ;947
000038  d002              BEQ      |L17.64|
00003a  4a15              LDR      r2,|L17.144|
00003c  42d1              CMN      r1,r2                 ;947
00003e  d103              BNE      |L17.72|
                  |L17.64|
000040  6871              LDR      r1,[r6,#4]            ;962
000042  6b8a              LDR      r2,[r1,#0x38]         ;950
000044  b96a              CBNZ     r2,|L17.98|
000046  e00b              B        |L17.96|
                  |L17.72|
000048  f7fffffe          BL       CPU_SR_Restore
00004c  f2427088          MOV      r0,#0x2788            ;956
000050  8020              STRH     r0,[r4,#0]            ;956
000052  2000              MOVS     r0,#0                 ;957
000054  e7e5              B        |L17.34|
                  |L17.86|
000056  f2427011          MOV      r0,#0x2711            ;939
00005a  8020              STRH     r0,[r4,#0]            ;939
00005c  2000              MOVS     r0,#0                 ;940
00005e  e7e0              B        |L17.34|
                  |L17.96|
000060  490c              LDR      r1,|L17.148|
                  |L17.98|
000062  6c4e              LDR      r6,[r1,#0x44]         ;965
000064  6bcf              LDR      r7,[r1,#0x3c]         ;966
000066  f7fffffe          BL       CPU_SR_Restore
00006a  2d01              CMP      r5,#1                 ;970
00006c  d908              BLS      |L17.128|
00006e  fbb7f0f5          UDIV     r0,r7,r5              ;971
000072  fb057010          MLS      r0,r5,r0,r7           ;971
000076  b108              CBZ      r0,|L17.124|
000078  1a28              SUBS     r0,r5,r0              ;972
00007a  e000              B        |L17.126|
                  |L17.124|
00007c  2000              MOVS     r0,#0                 ;972
                  |L17.126|
00007e  1a36              SUBS     r6,r6,r0              ;973
                  |L17.128|
000080  f2427010          MOV      r0,#0x2710            ;977
000084  8020              STRH     r0,[r4,#0]            ;977
000086  4630              MOV      r0,r6                 ;979
000088  e7cb              B        |L17.34|
;;;981    #endif
                          ENDP

00008a  0000              DCW      0x0000
                  |L17.140|
                          DCD      0xb3b0b0b0
                  |L17.144|
                          DCD      0xfc0e0a08
                  |L17.148|
                          DCD      ||.bss||

                          AREA ||i.Mem_Set||, CODE, READONLY, ALIGN=1

                  Mem_Set PROC
;;;268    
;;;269    void  Mem_Set (void        *pmem,
000000  b510              PUSH     {r4,lr}
;;;270                   CPU_INT08U   data_val,
;;;271                   CPU_SIZE_T   size)
;;;272    {
;;;273        CPU_SIZE_T   size_rem;
;;;274        CPU_ALIGN    data_align;
;;;275        CPU_ALIGN   *pmem_align;
;;;276        CPU_INT08U  *pmem_08;
;;;277        CPU_DATA     mem_align_mod;
;;;278        CPU_DATA     i;
;;;279    
;;;280    
;;;281    #if (LIB_MEM_CFG_ARG_CHK_EXT_EN == DEF_ENABLED)
;;;282        if (size < 1) {                                             /* See Note #1.                                         */
000002  2a00              CMP      r2,#0
000004  d01e              BEQ      |L18.68|
;;;283            return;
;;;284        }
;;;285        if (pmem == (void *)0) {
000006  2800              CMP      r0,#0
000008  d01c              BEQ      |L18.68|
;;;286            return;
;;;287        }
;;;288    #endif
;;;289    
;;;290    
;;;291        data_align = 0u;
00000a  2300              MOVS     r3,#0
;;;292        for (i = 0u; i < sizeof(CPU_ALIGN); i++) {                  /* Fill each data_align octet with data val.            */
00000c  2400              MOVS     r4,#0
                  |L18.14|
;;;293            data_align <<=  DEF_OCTET_NBR_BITS;
00000e  021b              LSLS     r3,r3,#8
;;;294            data_align  |= (CPU_ALIGN)data_val;
000010  430b              ORRS     r3,r3,r1
000012  1c64              ADDS     r4,r4,#1              ;292
000014  2c04              CMP      r4,#4                 ;292
000016  d3fa              BCC      |L18.14|
;;;295        }
;;;296    
;;;297        size_rem      =  size;
;;;298        mem_align_mod = (CPU_INT08U)((CPU_ADDR)pmem % sizeof(CPU_ALIGN));   /* See Note #3.                                 */
000018  f0000403          AND      r4,r0,#3
;;;299    
;;;300        pmem_08 = (CPU_INT08U *)pmem;
;;;301        if (mem_align_mod != 0u) {                                  /* If leading octets avail,                   ...       */
00001c  b924              CBNZ     r4,|L18.40|
00001e  e009              B        |L18.52|
                  |L18.32|
;;;302            i = mem_align_mod;
;;;303            while ((size_rem > 0) &&                                /* ... start mem buf fill with leading octets ...       */
;;;304                   (i        < sizeof(CPU_ALIGN ))) {               /* ... until next CPU_ALIGN word boundary.              */
;;;305               *pmem_08++ = data_val;
000020  f8001b01          STRB     r1,[r0],#1
;;;306                size_rem -= sizeof(CPU_INT08U);
000024  1e52              SUBS     r2,r2,#1
;;;307                i++;
000026  1c64              ADDS     r4,r4,#1
                  |L18.40|
000028  b122              CBZ      r2,|L18.52|
00002a  2c04              CMP      r4,#4                 ;304
00002c  d3f8              BCC      |L18.32|
00002e  e001              B        |L18.52|
                  |L18.48|
;;;308            }
;;;309        }
;;;310    
;;;311        pmem_align = (CPU_ALIGN *)pmem_08;                          /* See Note #2a.                                        */
;;;312        while (size_rem >= sizeof(CPU_ALIGN)) {                     /* While mem buf aligned on CPU_ALIGN word boundaries,  */
;;;313           *pmem_align++ = data_align;                              /* ... fill mem buf with    CPU_ALIGN-sized data.       */
000030  c008              STM      r0!,{r3}
;;;314            size_rem    -= sizeof(CPU_ALIGN);
000032  1f12              SUBS     r2,r2,#4
                  |L18.52|
000034  2a04              CMP      r2,#4                 ;312
000036  d2fb              BCS      |L18.48|
000038  e002              B        |L18.64|
                  |L18.58|
;;;315        }
;;;316    
;;;317        pmem_08 = (CPU_INT08U *)pmem_align;
;;;318        while (size_rem > 0) {                                      /* Finish mem buf fill with trailing octets.            */
;;;319           *pmem_08++   = data_val;
00003a  f8001b01          STRB     r1,[r0],#1
;;;320            size_rem   -= sizeof(CPU_INT08U);
00003e  1e52              SUBS     r2,r2,#1
                  |L18.64|
000040  2a00              CMP      r2,#0                 ;318
000042  d1fa              BNE      |L18.58|
                  |L18.68|
;;;321        }
;;;322    }
000044  bd10              POP      {r4,pc}
;;;323    
                          ENDP


                          AREA ||.bss||, DATA, NOINIT, ALIGN=2

                  Mem_PoolHeap
                          %        72
                  Mem_Heap
                          %        23552

                          AREA ||.data||, DATA, ALIGN=2

                  Mem_PoolTbl
                          DCD      0x00000000