AGV / agv_shengyiPPxiaoche · Files

; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\flash\obj\cpu_c.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\cpu_c.d --cpu=Cortex-M4.fp --apcs=interwork -O1 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Include -I..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\uCOS-III\uC-CPU -I..\..\uCOS-III\uC-LIB -I..\..\uCOS-III\uCOS-III\Ports -I..\..\uCOS-III\uCOS-III\Source -I..\..\uCOS-III\uC-CPU\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uC-LIB\Ports\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uCOS-III\Ports\ARM-Cortex-M4\Generic\RealView -I..\..\User -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\libapp -I..\..\RL-ARM\Config -I..\..\RL-ARM\Driver -I..\..\RL-ARM\RL-RTX\inc -I..\..\User\bsp\BSP -I..\..\RL-ARM\RL-CAN -I..\..\Libraries\DSP_LIB\Include -I..\..\MODBUS\modbus\rtu -I..\..\MODBUS\BARE\port -I..\..\MODBUS\modbus\include -I..\..\User\bsp\BSP -I..\..\PLC -I..\..\Avoid -I..\..\User\parameter -I..\..\User\LaserMotionCtr -I..\..\User\W5100S -I..\..\User\bsp -I..\..\User\CHASSIS -I..\..\User\CONTROLFUNCTION -I..\..\User\DATAUPDATE -I..\..\User\HARAWARE -I..\..\User\MOTORDRIVER -I..\..\User\NAVAGATION -I..\..\User\PLATFORM -I..\..\User\SENSOR -I.\RTE\_Flash -IC:\Users\YDJ\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include -IC:\Users\YDJ\AppData\Local\Arm\Packs\Keil\STM32F4xx_DFP\2.13.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include -D__UVISION_VERSION=527 -D_RTE_ -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -D__RTX -D__FPU_USED=1 --omf_browse=.\flash\obj\cpu_c.crf ..\..\uCOS-III\uC-CPU\ARM-Cortex-M4\RealView\cpu_c.c]
                          THUMB

                          AREA ||i.CPU_BitBandClr||, CODE, READONLY, ALIGN=1

                  CPU_BitBandClr PROC
;;;133    
;;;134    void  CPU_BitBandClr (CPU_ADDR    addr,
000000  b510              PUSH     {r4,lr}
;;;135                          CPU_INT08U  bit_nbr)
;;;136    {
;;;137        CPU_ADDR  bit_word_off;
;;;138        CPU_ADDR  bit_word_addr;
;;;139    
;;;140    
;;;141        if ((addr >= CPU_BIT_BAND_SRAM_REG_LO) &&
000002  f1a05200          SUB      r2,r0,#0x20000000
000006  f44f1480          MOV      r4,#0x100000
00000a  2300              MOVS     r3,#0
00000c  42a2              CMP      r2,r4
00000e  d206              BCS      |L1.30|
;;;142            (addr <= CPU_BIT_BAND_SRAM_REG_HI)) {
;;;143            bit_word_off  = ((addr - CPU_BIT_BAND_SRAM_REG_LO  ) * 32) + (bit_nbr * 4);
000010  0150              LSLS     r0,r2,#5
000012  eb000081          ADD      r0,r0,r1,LSL #2
;;;144            bit_word_addr = CPU_BIT_BAND_SRAM_BASE   + bit_word_off;
000016  f1005008          ADD      r0,r0,#0x22000000
;;;145    
;;;146          *(volatile CPU_INT32U *)(bit_word_addr) = 0;
00001a  6003              STR      r3,[r0,#0]
                  |L1.28|
;;;147    
;;;148        } else if ((addr >= CPU_BIT_BAND_PERIPH_REG_LO) &&
;;;149                   (addr <= CPU_BIT_BAND_PERIPH_REG_HI)) {
;;;150            bit_word_off  = ((addr - CPU_BIT_BAND_PERIPH_REG_LO) * 32) + (bit_nbr * 4);
;;;151            bit_word_addr = CPU_BIT_BAND_PERIPH_BASE + bit_word_off;
;;;152    
;;;153          *(volatile CPU_INT32U *)(bit_word_addr) = 0;
;;;154        }
;;;155    }
00001c  bd10              POP      {r4,pc}
                  |L1.30|
00001e  f1a04080          SUB      r0,r0,#0x40000000     ;148
000022  42a0              CMP      r0,r4                 ;148
000024  d2fa              BCS      |L1.28|
000026  0140              LSLS     r0,r0,#5              ;150
000028  eb000081          ADD      r0,r0,r1,LSL #2       ;150
00002c  f1004084          ADD      r0,r0,#0x42000000     ;151
000030  6003              STR      r3,[r0,#0]            ;153
000032  bd10              POP      {r4,pc}
;;;156    
                          ENDP


                          AREA ||i.CPU_BitBandSet||, CODE, READONLY, ALIGN=1

                  CPU_BitBandSet PROC
;;;176    
;;;177    void  CPU_BitBandSet (CPU_ADDR    addr,
000000  b510              PUSH     {r4,lr}
;;;178                          CPU_INT08U  bit_nbr)
;;;179    {
;;;180        CPU_ADDR  bit_word_off;
;;;181        CPU_ADDR  bit_word_addr;
;;;182    
;;;183    
;;;184        if ((addr >= CPU_BIT_BAND_SRAM_REG_LO) &&
000002  f1a05200          SUB      r2,r0,#0x20000000
000006  f44f1480          MOV      r4,#0x100000
;;;185            (addr <= CPU_BIT_BAND_SRAM_REG_HI)) {
;;;186            bit_word_off  = ((addr - CPU_BIT_BAND_SRAM_REG_LO  ) * 32) + (bit_nbr * 4);
;;;187            bit_word_addr = CPU_BIT_BAND_SRAM_BASE   + bit_word_off;
;;;188    
;;;189          *(volatile CPU_INT32U *)(bit_word_addr) = 1;
00000a  2301              MOVS     r3,#1
00000c  42a2              CMP      r2,r4                 ;184
00000e  d206              BCS      |L2.30|
000010  0150              LSLS     r0,r2,#5              ;186
000012  eb000081          ADD      r0,r0,r1,LSL #2       ;186
000016  f1005008          ADD      r0,r0,#0x22000000     ;187
00001a  6003              STR      r3,[r0,#0]
                  |L2.28|
;;;190    
;;;191        } else if ((addr >= CPU_BIT_BAND_PERIPH_REG_LO) &&
;;;192                   (addr <= CPU_BIT_BAND_PERIPH_REG_HI)) {
;;;193            bit_word_off  = ((addr - CPU_BIT_BAND_PERIPH_REG_LO) * 32) + (bit_nbr * 4);
;;;194            bit_word_addr = CPU_BIT_BAND_PERIPH_BASE + bit_word_off;
;;;195    
;;;196          *(volatile CPU_INT32U *)(bit_word_addr) = 1;
;;;197        }
;;;198    }
00001c  bd10              POP      {r4,pc}
                  |L2.30|
00001e  f1a04080          SUB      r0,r0,#0x40000000     ;191
000022  42a0              CMP      r0,r4                 ;191
000024  d2fa              BCS      |L2.28|
000026  0140              LSLS     r0,r0,#5              ;193
000028  eb000081          ADD      r0,r0,r1,LSL #2       ;193
00002c  f1004084          ADD      r0,r0,#0x42000000     ;194
000030  6003              STR      r3,[r0,#0]            ;196
000032  bd10              POP      {r4,pc}
;;;199    
                          ENDP


                          AREA ||i.CPU_IntSrcDis||, CODE, READONLY, ALIGN=2

                  CPU_IntSrcDis PROC
;;;250    /*$PAGE*/
;;;251    void  CPU_IntSrcDis (CPU_INT08U  pos)
000000  b570              PUSH     {r4-r6,lr}
;;;252    {
;;;253        CPU_INT08U  group;
;;;254        CPU_INT08U  pos_max;
;;;255        CPU_INT08U  nbr;
;;;256        CPU_SR_ALLOC();
;;;257    
;;;258    
;;;259        switch (pos) {
;;;260            case CPU_INT_STK_PTR:                                   /* ---------------- INVALID OR RESERVED --------------- */
;;;261            case CPU_INT_RSVD_07:
;;;262            case CPU_INT_RSVD_08:
;;;263            case CPU_INT_RSVD_09:
;;;264            case CPU_INT_RSVD_10:
;;;265            case CPU_INT_RSVD_13:
;;;266                 break;
;;;267    
;;;268    
;;;269                                                                    /* ----------------- SYSTEM EXCEPTIONS ---------------- */
;;;270            case CPU_INT_RESET:                                     /* Reset (see Note #2).                                 */
;;;271            case CPU_INT_NMI:                                       /* Non-maskable interrupt (see Note #2).                */
;;;272            case CPU_INT_HFAULT:                                    /* Hard fault (see Note #2).                            */
;;;273            case CPU_INT_SVCALL:                                    /* SVCall (see Note #2).                                */
;;;274            case CPU_INT_DBGMON:                                    /* Debug monitor (see Note #2).                         */
;;;275            case CPU_INT_PENDSV:                                    /* PendSV (see Note #2).                                */
;;;276                 break;
;;;277    
;;;278            case CPU_INT_MEM:                                       /* Memory management.                                   */
;;;279                 CPU_CRITICAL_ENTER();
;;;280                 CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_MEMFAULTENA;
000002  4c2b              LDR      r4,|L3.176|
;;;281                 CPU_CRITICAL_EXIT();
;;;282                 break;
;;;283    
;;;284            case CPU_INT_BUSFAULT:                                  /* Bus fault.                                           */
;;;285                 CPU_CRITICAL_ENTER();
;;;286                 CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_BUSFAULTENA;
;;;287                 CPU_CRITICAL_EXIT();
;;;288                 break;
;;;289    
;;;290            case CPU_INT_USAGEFAULT:                                /* Usage fault.                                         */
;;;291                 CPU_CRITICAL_ENTER();
;;;292                 CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_USGFAULTENA;
;;;293                 CPU_CRITICAL_EXIT();
;;;294                 break;
;;;295    
;;;296            case CPU_INT_SYSTICK:                                   /* SysTick.                                             */
;;;297                 CPU_CRITICAL_ENTER();
;;;298                 CPU_REG_NVIC_ST_CTRL &= ~CPU_REG_NVIC_ST_CTRL_ENABLE;
000004  f04f25e0          MOV      r5,#0xe000e000
000008  2810              CMP      r0,#0x10              ;259
00000a  d231              BCS      |L3.112|
00000c  e8dff000          TBB      [pc,r0]               ;259
000010  4e4e4e4e          DCB      0x4e,0x4e,0x4e,0x4e
000014  08121c4e          DCB      0x08,0x12,0x1c,0x4e
000018  4e4e4e4e          DCB      0x4e,0x4e,0x4e,0x4e
00001c  4e4e4e26          DCB      0x4e,0x4e,0x4e,0x26
000020  f7fffffe          BL       CPU_SR_Save
000024  6821              LDR      r1,[r4,#0]            ;280
000026  f4213180          BIC      r1,r1,#0x10000        ;280
00002a  6021              STR      r1,[r4,#0]            ;280
00002c  e8bd4070          POP      {r4-r6,lr}            ;281
000030  f7ffbffe          B.W      CPU_SR_Restore
000034  f7fffffe          BL       CPU_SR_Save
000038  6821              LDR      r1,[r4,#0]            ;286
00003a  f4213100          BIC      r1,r1,#0x20000        ;286
00003e  6021              STR      r1,[r4,#0]            ;286
000040  e8bd4070          POP      {r4-r6,lr}            ;287
000044  f7ffbffe          B.W      CPU_SR_Restore
000048  f7fffffe          BL       CPU_SR_Save
00004c  6821              LDR      r1,[r4,#0]            ;292
00004e  f4212180          BIC      r1,r1,#0x40000        ;292
000052  6021              STR      r1,[r4,#0]            ;292
000054  e8bd4070          POP      {r4-r6,lr}            ;293
000058  f7ffbffe          B.W      CPU_SR_Restore
00005c  f7fffffe          BL       CPU_SR_Save
000060  6929              LDR      r1,[r5,#0x10]
000062  f0210101          BIC      r1,r1,#1
000066  6129              STR      r1,[r5,#0x10]
;;;299                 CPU_CRITICAL_EXIT();
000068  e8bd4070          POP      {r4-r6,lr}
00006c  f7ffbffe          B.W      CPU_SR_Restore
                  |L3.112|
;;;300                 break;
;;;301    
;;;302    
;;;303                                                                    /* ---------------- EXTERNAL INTERRUPT ---------------- */
;;;304            default:
;;;305                pos_max = CPU_INT_SRC_POS_MAX;
000070  6869              LDR      r1,[r5,#4]
000072  1c49              ADDS     r1,r1,#1
000074  2210              MOVS     r2,#0x10
000076  eb021141          ADD      r1,r2,r1,LSL #5
00007a  b2c9              UXTB     r1,r1
;;;306                if (pos < pos_max) {                                /* See Note #3.                                         */
00007c  4288              CMP      r0,r1
00007e  d215              BCS      |L3.172|
;;;307                     group = (pos - 16) / 32;
000080  3810              SUBS     r0,r0,#0x10
000082  17c1              ASRS     r1,r0,#31
000084  eb0061d1          ADD      r1,r0,r1,LSR #27
000088  f3c11547          UBFX     r5,r1,#5,#8
;;;308                     nbr   = (pos - 16) % 32;
00008c  f021011f          BIC      r1,r1,#0x1f
000090  1a44              SUBS     r4,r0,r1
;;;309    
;;;310                     CPU_CRITICAL_ENTER();
000092  f7fffffe          BL       CPU_SR_Save
;;;311                     CPU_REG_NVIC_CLREN(group) = DEF_BIT(nbr);
000096  2101              MOVS     r1,#1
000098  40a1              LSLS     r1,r1,r4
00009a  00aa              LSLS     r2,r5,#2
00009c  f10222e0          ADD      r2,r2,#0xe000e000
0000a0  f8c21180          STR      r1,[r2,#0x180]
;;;312                     CPU_CRITICAL_EXIT();
0000a4  e8bd4070          POP      {r4-r6,lr}
0000a8  f7ffbffe          B.W      CPU_SR_Restore
                  |L3.172|
;;;313                 }
;;;314                 break;
;;;315        }
;;;316    }
0000ac  bd70              POP      {r4-r6,pc}
;;;317    
                          ENDP

0000ae  0000              DCW      0x0000
                  |L3.176|
                          DCD      0xe000ed24

                          AREA ||i.CPU_IntSrcEn||, CODE, READONLY, ALIGN=2

                  CPU_IntSrcEn PROC
;;;339    
;;;340    void  CPU_IntSrcEn (CPU_INT08U  pos)
000000  b570              PUSH     {r4-r6,lr}
;;;341    {
;;;342        CPU_INT08U  group;
;;;343        CPU_INT08U  nbr;
;;;344        CPU_INT08U  pos_max;
;;;345        CPU_SR_ALLOC();
;;;346    
;;;347    
;;;348        switch (pos) {
;;;349            case CPU_INT_STK_PTR:                                   /* ---------------- INVALID OR RESERVED --------------- */
;;;350            case CPU_INT_RSVD_07:
;;;351            case CPU_INT_RSVD_08:
;;;352            case CPU_INT_RSVD_09:
;;;353            case CPU_INT_RSVD_10:
;;;354            case CPU_INT_RSVD_13:
;;;355                 break;
;;;356    
;;;357    
;;;358                                                                    /* ----------------- SYSTEM EXCEPTIONS ---------------- */
;;;359            case CPU_INT_RESET:                                     /* Reset (see Note #2).                                 */
;;;360            case CPU_INT_NMI:                                       /* Non-maskable interrupt (see Note #2).                */
;;;361            case CPU_INT_HFAULT:                                    /* Hard fault (see Note #2).                            */
;;;362            case CPU_INT_SVCALL:                                    /* SVCall (see Note #2).                                */
;;;363            case CPU_INT_DBGMON:                                    /* Debug monitor (see Note #2).                         */
;;;364            case CPU_INT_PENDSV:                                    /* PendSV (see Note #2).                                */
;;;365                 break;
;;;366    
;;;367            case CPU_INT_MEM:                                       /* Memory management.                                   */
;;;368                 CPU_CRITICAL_ENTER();
;;;369                 CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_MEMFAULTENA;
000002  4c2b              LDR      r4,|L4.176|
;;;370                 CPU_CRITICAL_EXIT();
;;;371                 break;
;;;372    
;;;373            case CPU_INT_BUSFAULT:                                  /* Bus fault.                                           */
;;;374                 CPU_CRITICAL_ENTER();
;;;375                 CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_BUSFAULTENA;
;;;376                 CPU_CRITICAL_EXIT();
;;;377                 break;
;;;378    
;;;379            case CPU_INT_USAGEFAULT:                                /* Usage fault.                                         */
;;;380                 CPU_CRITICAL_ENTER();
;;;381                 CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_USGFAULTENA;
;;;382                 CPU_CRITICAL_EXIT();
;;;383                 break;
;;;384    
;;;385            case CPU_INT_SYSTICK:                                   /* SysTick.                                             */
;;;386                 CPU_CRITICAL_ENTER();
;;;387                 CPU_REG_NVIC_ST_CTRL |= CPU_REG_NVIC_ST_CTRL_ENABLE;
000004  f04f25e0          MOV      r5,#0xe000e000
000008  2810              CMP      r0,#0x10              ;348
00000a  d231              BCS      |L4.112|
00000c  e8dff000          TBB      [pc,r0]               ;348
000010  4e4e4e4e          DCB      0x4e,0x4e,0x4e,0x4e
000014  08121c4e          DCB      0x08,0x12,0x1c,0x4e
000018  4e4e4e4e          DCB      0x4e,0x4e,0x4e,0x4e
00001c  4e4e4e26          DCB      0x4e,0x4e,0x4e,0x26
000020  f7fffffe          BL       CPU_SR_Save
000024  6821              LDR      r1,[r4,#0]            ;369
000026  f4413180          ORR      r1,r1,#0x10000        ;369
00002a  6021              STR      r1,[r4,#0]            ;369
00002c  e8bd4070          POP      {r4-r6,lr}            ;370
000030  f7ffbffe          B.W      CPU_SR_Restore
000034  f7fffffe          BL       CPU_SR_Save
000038  6821              LDR      r1,[r4,#0]            ;375
00003a  f4413100          ORR      r1,r1,#0x20000        ;375
00003e  6021              STR      r1,[r4,#0]            ;375
000040  e8bd4070          POP      {r4-r6,lr}            ;376
000044  f7ffbffe          B.W      CPU_SR_Restore
000048  f7fffffe          BL       CPU_SR_Save
00004c  6821              LDR      r1,[r4,#0]            ;381
00004e  f4412180          ORR      r1,r1,#0x40000        ;381
000052  6021              STR      r1,[r4,#0]            ;381
000054  e8bd4070          POP      {r4-r6,lr}            ;382
000058  f7ffbffe          B.W      CPU_SR_Restore
00005c  f7fffffe          BL       CPU_SR_Save
000060  6929              LDR      r1,[r5,#0x10]
000062  f0410101          ORR      r1,r1,#1
000066  6129              STR      r1,[r5,#0x10]
;;;388                 CPU_CRITICAL_EXIT();
000068  e8bd4070          POP      {r4-r6,lr}
00006c  f7ffbffe          B.W      CPU_SR_Restore
                  |L4.112|
;;;389                 break;
;;;390    
;;;391    
;;;392                                                                    /* ---------------- EXTERNAL INTERRUPT ---------------- */
;;;393            default:
;;;394                pos_max = CPU_INT_SRC_POS_MAX;
000070  6869              LDR      r1,[r5,#4]
000072  1c49              ADDS     r1,r1,#1
000074  2210              MOVS     r2,#0x10
000076  eb021141          ADD      r1,r2,r1,LSL #5
00007a  b2c9              UXTB     r1,r1
;;;395                if (pos < pos_max) {                                /* See Note #3.                                         */
00007c  4288              CMP      r0,r1
00007e  d215              BCS      |L4.172|
;;;396                     group = (pos - 16) / 32;
000080  3810              SUBS     r0,r0,#0x10
000082  17c1              ASRS     r1,r0,#31
000084  eb0061d1          ADD      r1,r0,r1,LSR #27
000088  f3c11547          UBFX     r5,r1,#5,#8
;;;397                     nbr   = (pos - 16) % 32;
00008c  f021011f          BIC      r1,r1,#0x1f
000090  1a44              SUBS     r4,r0,r1
;;;398    
;;;399                     CPU_CRITICAL_ENTER();
000092  f7fffffe          BL       CPU_SR_Save
;;;400                     CPU_REG_NVIC_SETEN(group) = DEF_BIT(nbr);
000096  2101              MOVS     r1,#1
000098  40a1              LSLS     r1,r1,r4
00009a  00aa              LSLS     r2,r5,#2
00009c  f10222e0          ADD      r2,r2,#0xe000e000
0000a0  f8c21100          STR      r1,[r2,#0x100]
;;;401                     CPU_CRITICAL_EXIT();
0000a4  e8bd4070          POP      {r4-r6,lr}
0000a8  f7ffbffe          B.W      CPU_SR_Restore
                  |L4.172|
;;;402                 }
;;;403                 break;
;;;404        }
;;;405    }
0000ac  bd70              POP      {r4-r6,pc}
;;;406    
                          ENDP

0000ae  0000              DCW      0x0000
                  |L4.176|
                          DCD      0xe000ed24

                          AREA ||i.CPU_IntSrcPendClr||, CODE, READONLY, ALIGN=1

                  CPU_IntSrcPendClr PROC
;;;438    
;;;439    void  CPU_IntSrcPendClr (CPU_INT08U  pos)
000000  b570              PUSH     {r4-r6,lr}
;;;440    
;;;441    {
;;;442        CPU_INT08U  group;
;;;443        CPU_INT08U  nbr;
;;;444        CPU_INT08U  pos_max;
;;;445        CPU_SR_ALLOC();
;;;446    
;;;447    
;;;448        switch (pos) {
000002  280f              CMP      r0,#0xf
000004  d91f              BLS      |L5.70|
;;;449            case CPU_INT_STK_PTR:                                   /* ---------------- INVALID OR RESERVED --------------- */
;;;450            case CPU_INT_RSVD_07:
;;;451            case CPU_INT_RSVD_08:
;;;452            case CPU_INT_RSVD_09:
;;;453            case CPU_INT_RSVD_10:
;;;454            case CPU_INT_RSVD_13:
;;;455                 break;
;;;456                                                                    /* ----------------- SYSTEM EXCEPTIONS ---------------- */
;;;457            case CPU_INT_RESET:                                     /* Reset (see Note #2).                                 */
;;;458            case CPU_INT_NMI:                                       /* Non-maskable interrupt (see Note #2).                */
;;;459            case CPU_INT_HFAULT:                                    /* Hard fault (see Note #2).                            */
;;;460            case CPU_INT_MEM:                                       /* Memory management (see Note #2).                     */
;;;461            case CPU_INT_SVCALL:                                    /* SVCall (see Note #2).                                */
;;;462            case CPU_INT_DBGMON:                                    /* Debug monitor (see Note #2).                         */
;;;463            case CPU_INT_PENDSV:                                    /* PendSV (see Note #2).                                */
;;;464            case CPU_INT_BUSFAULT:                                  /* Bus fault.                                           */
;;;465            case CPU_INT_USAGEFAULT:                                /* Usage fault.                                         */
;;;466            case CPU_INT_SYSTICK:                                   /* SysTick.                                             */
;;;467                 break;
;;;468                                                                    /* ---------------- EXTERNAL INTERRUPT ---------------- */
;;;469            default:
;;;470                pos_max = CPU_INT_SRC_POS_MAX;
000006  f04f21e0          MOV      r1,#0xe000e000
00000a  6849              LDR      r1,[r1,#4]
00000c  1c49              ADDS     r1,r1,#1
00000e  2210              MOVS     r2,#0x10
000010  eb021141          ADD      r1,r2,r1,LSL #5
000014  b2c9              UXTB     r1,r1
;;;471                if (pos < pos_max) {                                /* See Note #3.                                         */
000016  4288              CMP      r0,r1
000018  d215              BCS      |L5.70|
;;;472                     group = (pos - 16) / 32;
00001a  3810              SUBS     r0,r0,#0x10
00001c  17c1              ASRS     r1,r0,#31
00001e  eb0061d1          ADD      r1,r0,r1,LSR #27
000022  f3c11547          UBFX     r5,r1,#5,#8
;;;473                     nbr   = (pos - 16) % 32;
000026  f021011f          BIC      r1,r1,#0x1f
00002a  1a44              SUBS     r4,r0,r1
;;;474    
;;;475                     CPU_CRITICAL_ENTER();
00002c  f7fffffe          BL       CPU_SR_Save
;;;476                     CPU_REG_NVIC_CLRPEND(group) = DEF_BIT(nbr);
000030  2101              MOVS     r1,#1
000032  40a1              LSLS     r1,r1,r4
000034  00aa              LSLS     r2,r5,#2
000036  f10222e0          ADD      r2,r2,#0xe000e000
00003a  f8c21280          STR      r1,[r2,#0x280]
;;;477                     CPU_CRITICAL_EXIT();
00003e  e8bd4070          POP      {r4-r6,lr}
000042  f7ffbffe          B.W      CPU_SR_Restore
                  |L5.70|
;;;478                 }
;;;479                 break;
;;;480        }
;;;481    }
000046  bd70              POP      {r4-r6,pc}
;;;482    
                          ENDP


                          AREA ||i.CPU_IntSrcPrioGet||, CODE, READONLY, ALIGN=2

                  CPU_IntSrcPrioGet PROC
;;;645    
;;;646    CPU_INT16S  CPU_IntSrcPrioGet (CPU_INT08U  pos)
000000  b570              PUSH     {r4-r6,lr}
;;;647    {
;;;648        CPU_INT08U  group;
;;;649        CPU_INT08U  nbr;
;;;650        CPU_INT08U  pos_max;
;;;651        CPU_INT16S  prio;
;;;652        CPU_INT32U  prio_32;
;;;653        CPU_INT32U  temp;
;;;654        CPU_SR_ALLOC();
;;;655    
;;;656    
;;;657        switch (pos) {
;;;658            case CPU_INT_STK_PTR:                                   /* ---------------- INVALID OR RESERVED --------------- */
;;;659            case CPU_INT_RSVD_07:
;;;660            case CPU_INT_RSVD_08:
;;;661            case CPU_INT_RSVD_09:
;;;662            case CPU_INT_RSVD_10:
;;;663            case CPU_INT_RSVD_13:
;;;664                 prio = DEF_INT_16S_MIN_VAL;
;;;665                 break;
;;;666    
;;;667    
;;;668                                                                    /* ----------------- SYSTEM EXCEPTIONS ---------------- */
;;;669            case CPU_INT_RESET:                                     /* Reset (see Note #2).                                 */
;;;670                 prio = -3;
;;;671                 break;
;;;672    
;;;673            case CPU_INT_NMI:                                       /* Non-maskable interrupt (see Note #2).                */
;;;674                 prio = -2;
;;;675                 break;
;;;676    
;;;677            case CPU_INT_HFAULT:                                    /* Hard fault (see Note #2).                            */
;;;678                 prio = -1;
;;;679                 break;
;;;680    
;;;681    
;;;682            case CPU_INT_MEM:                                       /* Memory management.                                   */
;;;683                 CPU_CRITICAL_ENTER();
;;;684                 temp = CPU_REG_NVIC_SHPRI1;
;;;685                 prio = (temp >> (0 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
;;;686                 CPU_CRITICAL_EXIT();
;;;687                 break;
;;;688    
;;;689    
;;;690            case CPU_INT_BUSFAULT:                                  /* Bus fault.                                           */
;;;691                 CPU_CRITICAL_ENTER();
;;;692                 temp = CPU_REG_NVIC_SHPRI1;
;;;693                 prio = (temp >> (1 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
;;;694                 CPU_CRITICAL_EXIT();
;;;695                 break;
;;;696    
;;;697    
;;;698            case CPU_INT_USAGEFAULT:                                /* Usage fault.                                         */
;;;699                 CPU_CRITICAL_ENTER();
;;;700                 temp = CPU_REG_NVIC_SHPRI1;
;;;701                 prio = (temp >> (2 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
;;;702                 break;
;;;703    
;;;704            case CPU_INT_SVCALL:                                    /* SVCall.                                              */
;;;705                 CPU_CRITICAL_ENTER();
;;;706                 temp = CPU_REG_NVIC_SHPRI2;
;;;707                 prio = (temp >> (3 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
;;;708                 CPU_CRITICAL_EXIT();
;;;709                 break;
;;;710    
;;;711            case CPU_INT_DBGMON:                                    /* Debug monitor.                                       */
;;;712                 CPU_CRITICAL_ENTER();
;;;713                 temp = CPU_REG_NVIC_SHPRI3;
000002  4e3b              LDR      r6,|L6.240|
000004  4c39              LDR      r4,|L6.236|
000006  4d3a              LDR      r5,|L6.240|
000008  3608              ADDS     r6,r6,#8
00000a  2810              CMP      r0,#0x10              ;657
00000c  d246              BCS      |L6.156|
00000e  e8dff000          TBB      [pc,r0]               ;657
000012  6408              DCB      0x64,0x08
000014  0b0e1118          DCB      0x0b,0x0e,0x11,0x18
000018  20646464          DCB      0x20,0x64,0x64,0x64
00001c  64262f64          DCB      0x64,0x26,0x2f,0x64
000020  363e              DCB      0x36,0x3e
000022  f06f0402          MVN      r4,#2                 ;670
000026  e058              B        |L6.218|
000028  f06f0401          MVN      r4,#1                 ;674
00002c  e055              B        |L6.218|
00002e  f04f34ff          MOV      r4,#0xffffffff        ;678
000032  e052              B        |L6.218|
000034  f7fffffe          BL       CPU_SR_Save
000038  6829              LDR      r1,[r5,#0]            ;684
00003a  b2cc              UXTB     r4,r1                 ;685
00003c  f7fffffe          BL       CPU_SR_Restore
000040  e04b              B        |L6.218|
000042  f7fffffe          BL       CPU_SR_Save
000046  6829              LDR      r1,[r5,#0]            ;692
000048  f3c12407          UBFX     r4,r1,#8,#8           ;693
00004c  f7fffffe          BL       CPU_SR_Restore
000050  e043              B        |L6.218|
000052  f7fffffe          BL       CPU_SR_Save
000056  6828              LDR      r0,[r5,#0]            ;700
000058  f3c04407          UBFX     r4,r0,#16,#8          ;701
00005c  e03d              B        |L6.218|
00005e  f7fffffe          BL       CPU_SR_Save
000062  4923              LDR      r1,|L6.240|
000064  1d09              ADDS     r1,r1,#4              ;706
000066  6809              LDR      r1,[r1,#0]            ;706
000068  0e0c              LSRS     r4,r1,#24             ;707
00006a  f7fffffe          BL       CPU_SR_Restore
00006e  e034              B        |L6.218|
000070  f7fffffe          BL       CPU_SR_Save
000074  6831              LDR      r1,[r6,#0]
;;;714                 prio = (temp >> (0 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
000076  b2cc              UXTB     r4,r1
;;;715                 CPU_CRITICAL_EXIT();
000078  f7fffffe          BL       CPU_SR_Restore
;;;716                 break;
00007c  e02d              B        |L6.218|
;;;717    
;;;718            case CPU_INT_PENDSV:                                    /* PendSV.                                              */
;;;719                 CPU_CRITICAL_ENTER();
00007e  f7fffffe          BL       CPU_SR_Save
;;;720                 temp = CPU_REG_NVIC_SHPRI3;
000082  6831              LDR      r1,[r6,#0]
;;;721                 prio = (temp >> (2 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
000084  f3c14407          UBFX     r4,r1,#16,#8
;;;722                 CPU_CRITICAL_EXIT();
000088  f7fffffe          BL       CPU_SR_Restore
;;;723                 break;
00008c  e025              B        |L6.218|
;;;724    
;;;725            case CPU_INT_SYSTICK:                                   /* SysTick.                                             */
;;;726                 CPU_CRITICAL_ENTER();
00008e  f7fffffe          BL       CPU_SR_Save
;;;727                 temp = CPU_REG_NVIC_SHPRI3;
000092  6831              LDR      r1,[r6,#0]
;;;728                 prio = (temp >> (3 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
000094  0e0c              LSRS     r4,r1,#24
;;;729                 CPU_CRITICAL_EXIT();
000096  f7fffffe          BL       CPU_SR_Restore
;;;730                 break;
00009a  e01e              B        |L6.218|
                  |L6.156|
;;;731    
;;;732    
;;;733                                                                    /* ---------------- EXTERNAL INTERRUPT ---------------- */
;;;734            default:
;;;735                pos_max = CPU_INT_SRC_POS_MAX;
00009c  f04f21e0          MOV      r1,#0xe000e000
0000a0  6849              LDR      r1,[r1,#4]
0000a2  1c49              ADDS     r1,r1,#1
0000a4  2210              MOVS     r2,#0x10
0000a6  eb021141          ADD      r1,r2,r1,LSL #5
0000aa  b2c9              UXTB     r1,r1
;;;736                if (pos < pos_max) {                                /* See Note #3.                                         */
0000ac  4288              CMP      r0,r1
0000ae  d214              BCS      |L6.218|
;;;737                     group = (pos - 16) / 4;
0000b0  3810              SUBS     r0,r0,#0x10
0000b2  17c1              ASRS     r1,r0,#31
0000b4  eb007191          ADD      r1,r0,r1,LSR #30
0000b8  f3c10587          UBFX     r5,r1,#2,#8
;;;738                     nbr   = (pos - 16) % 4;
0000bc  f0210103          BIC      r1,r1,#3
0000c0  1a44              SUBS     r4,r0,r1
;;;739    
;;;740                     CPU_CRITICAL_ENTER();
0000c2  f7fffffe          BL       CPU_SR_Save
;;;741                     temp  = CPU_REG_NVIC_PRIO(group);
0000c6  00a9              LSLS     r1,r5,#2
0000c8  f10121e0          ADD      r1,r1,#0xe000e000
0000cc  f8d15400          LDR      r5,[r1,#0x400]
;;;742                     CPU_CRITICAL_EXIT();
0000d0  f7fffffe          BL       CPU_SR_Restore
;;;743    
;;;744                     prio  = (temp >> (nbr * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
0000d4  00e0              LSLS     r0,r4,#3
0000d6  40c5              LSRS     r5,r5,r0
0000d8  b2ec              UXTB     r4,r5
                  |L6.218|
;;;745                 } else {
;;;746                     prio  = DEF_INT_16S_MIN_VAL;
;;;747                 }
;;;748                 break;
;;;749        }
;;;750    
;;;751        if (prio >= 0) {
0000da  2c00              CMP      r4,#0
0000dc  db03              BLT      |L6.230|
;;;752            prio_32 = CPU_RevBits((CPU_INT32U)prio);
0000de  4620              MOV      r0,r4
0000e0  f7fffffe          BL       CPU_RevBits
;;;753            prio    = (CPU_INT16S)(prio_32 >> (3 * DEF_OCTET_NBR_BITS));
0000e4  0e04              LSRS     r4,r0,#24
                  |L6.230|
;;;754        }
;;;755    
;;;756        return (prio);
0000e6  4620              MOV      r0,r4
;;;757    }
0000e8  bd70              POP      {r4-r6,pc}
;;;758    
                          ENDP

0000ea  0000              DCW      0x0000
                  |L6.236|
                          DCD      0xffff8000
                  |L6.240|
                          DCD      0xe000ed18

                          AREA ||i.CPU_IntSrcPrioSet||, CODE, READONLY, ALIGN=2

                  CPU_IntSrcPrioSet PROC
;;;510    
;;;511    void  CPU_IntSrcPrioSet (CPU_INT08U  pos,
000000  e92d41f0          PUSH     {r4-r8,lr}
;;;512                             CPU_INT08U  prio)
;;;513    {
000004  4605              MOV      r5,r0
000006  4608              MOV      r0,r1
;;;514        CPU_INT08U  group;
;;;515        CPU_INT08U  nbr;
;;;516        CPU_INT08U  pos_max;
;;;517        CPU_INT32U  prio_32;
;;;518        CPU_INT32U  temp;
;;;519        CPU_SR_ALLOC();
;;;520    
;;;521    
;;;522        prio_32 = CPU_RevBits((CPU_INT08U)prio);
000008  f7fffffe          BL       CPU_RevBits
;;;523        prio    = (CPU_INT08U)(prio_32 >> (3 * DEF_OCTET_NBR_BITS));
00000c  0e04              LSRS     r4,r0,#24
;;;524    
;;;525        switch (pos) {
;;;526            case CPU_INT_STK_PTR:                                   /* ---------------- INVALID OR RESERVED --------------- */
;;;527            case CPU_INT_RSVD_07:
;;;528            case CPU_INT_RSVD_08:
;;;529            case CPU_INT_RSVD_09:
;;;530            case CPU_INT_RSVD_10:
;;;531            case CPU_INT_RSVD_13:
;;;532                 break;
;;;533    
;;;534    
;;;535                                                                    /* ----------------- SYSTEM EXCEPTIONS ---------------- */
;;;536            case CPU_INT_RESET:                                     /* Reset (see Note #2).                                 */
;;;537            case CPU_INT_NMI:                                       /* Non-maskable interrupt (see Note #2).                */
;;;538            case CPU_INT_HFAULT:                                    /* Hard fault (see Note #2).                            */
;;;539                 break;
;;;540    
;;;541            case CPU_INT_MEM:                                       /* Memory management.                                   */
;;;542                 CPU_CRITICAL_ENTER();
;;;543                 temp                 = CPU_REG_NVIC_SHPRI1;
;;;544                 temp                &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
;;;545                 temp                |=  (prio           << (0 * DEF_OCTET_NBR_BITS));
;;;546                 CPU_REG_NVIC_SHPRI1  = temp;
;;;547                 CPU_CRITICAL_EXIT();
;;;548                 break;
;;;549    
;;;550            case CPU_INT_BUSFAULT:                                  /* Bus fault.                                           */
;;;551                 CPU_CRITICAL_ENTER();
;;;552                 temp                 = CPU_REG_NVIC_SHPRI1;
;;;553                 temp                &= ~(DEF_OCTET_MASK << (1 * DEF_OCTET_NBR_BITS));
;;;554                 temp                |=  (prio           << (1 * DEF_OCTET_NBR_BITS));
;;;555                 CPU_REG_NVIC_SHPRI1  = temp;
;;;556                 CPU_CRITICAL_EXIT();
;;;557                 break;
;;;558    
;;;559            case CPU_INT_USAGEFAULT:                                /* Usage fault.                                         */
;;;560                 CPU_CRITICAL_ENTER();
;;;561                 temp                 = CPU_REG_NVIC_SHPRI1;
;;;562                 temp                &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
;;;563                 temp                |=  (prio           << (2 * DEF_OCTET_NBR_BITS));
;;;564                 CPU_REG_NVIC_SHPRI1  = temp;
;;;565                 CPU_CRITICAL_EXIT();
;;;566                 break;
;;;567    
;;;568            case CPU_INT_SVCALL:                                    /* SVCall.                                              */
;;;569                 CPU_CRITICAL_ENTER();
;;;570                 temp                 = CPU_REG_NVIC_SHPRI2;
;;;571                 temp                &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
;;;572                 temp                |=  (prio                       << (3 * DEF_OCTET_NBR_BITS));
;;;573                 CPU_REG_NVIC_SHPRI2  = temp;
;;;574                 CPU_CRITICAL_EXIT();
;;;575                 break;
;;;576    
;;;577            case CPU_INT_DBGMON:                                    /* Debug monitor.                                       */
;;;578                 CPU_CRITICAL_ENTER();
;;;579                 temp                = CPU_REG_NVIC_SHPRI3;
00000e  4f45              LDR      r7,|L7.292|
000010  4e44              LDR      r6,|L7.292|
000012  3708              ADDS     r7,r7,#8
000014  2d10              CMP      r5,#0x10              ;525
000016  d25d              BCS      |L7.212|
000018  e8dff005          TBB      [pc,r5]               ;525
00001c  82828282          DCB      0x82,0x82,0x82,0x82
000020  08131f82          DCB      0x08,0x13,0x1f,0x82
000024  8282822b          DCB      0x82,0x82,0x82,0x2b
000028  39824450          DCB      0x39,0x82,0x44,0x50
00002c  f7fffffe          BL       CPU_SR_Save
000030  6831              LDR      r1,[r6,#0]            ;543
000032  f02101ff          BIC      r1,r1,#0xff           ;544
000036  4321              ORRS     r1,r1,r4              ;545
000038  6031              STR      r1,[r6,#0]            ;546
00003a  e8bd41f0          POP      {r4-r8,lr}            ;547
00003e  f7ffbffe          B.W      CPU_SR_Restore
000042  f7fffffe          BL       CPU_SR_Save
000046  6831              LDR      r1,[r6,#0]            ;552
000048  f421417f          BIC      r1,r1,#0xff00         ;553
00004c  ea412104          ORR      r1,r1,r4,LSL #8       ;554
000050  6031              STR      r1,[r6,#0]            ;555
000052  e8bd41f0          POP      {r4-r8,lr}            ;556
000056  f7ffbffe          B.W      CPU_SR_Restore
00005a  f7fffffe          BL       CPU_SR_Save
00005e  6831              LDR      r1,[r6,#0]            ;561
000060  f421017f          BIC      r1,r1,#0xff0000       ;562
000064  ea414104          ORR      r1,r1,r4,LSL #16      ;563
000068  6031              STR      r1,[r6,#0]            ;564
00006a  e8bd41f0          POP      {r4-r8,lr}            ;565
00006e  f7ffbffe          B.W      CPU_SR_Restore
000072  f7fffffe          BL       CPU_SR_Save
000076  4a2b              LDR      r2,|L7.292|
000078  1d12              ADDS     r2,r2,#4              ;570
00007a  6811              LDR      r1,[r2,#0]            ;570
00007c  f021417f          BIC      r1,r1,#0xff000000     ;571
000080  ea416104          ORR      r1,r1,r4,LSL #24      ;572
000084  6011              STR      r1,[r2,#0]            ;573
000086  e8bd41f0          POP      {r4-r8,lr}            ;574
00008a  f7ffbffe          B.W      CPU_SR_Restore
00008e  f7fffffe          BL       CPU_SR_Save
000092  6839              LDR      r1,[r7,#0]
;;;580                 temp                &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
000094  f02101ff          BIC      r1,r1,#0xff
;;;581                 temp                |=  (prio           << (0 * DEF_OCTET_NBR_BITS));
000098  4321              ORRS     r1,r1,r4
;;;582                 CPU_REG_NVIC_SHPRI3  = temp;
00009a  6039              STR      r1,[r7,#0]
;;;583                 CPU_CRITICAL_EXIT();
00009c  e8bd41f0          POP      {r4-r8,lr}
0000a0  f7ffbffe          B.W      CPU_SR_Restore
;;;584                 break;
;;;585    
;;;586            case CPU_INT_PENDSV:                                    /* PendSV.                                              */
;;;587                 CPU_CRITICAL_ENTER();
0000a4  f7fffffe          BL       CPU_SR_Save
;;;588                 temp                 = CPU_REG_NVIC_SHPRI3;
0000a8  6839              LDR      r1,[r7,#0]
;;;589                 temp                &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
0000aa  f421017f          BIC      r1,r1,#0xff0000
;;;590                 temp                |=  (prio           << (2 * DEF_OCTET_NBR_BITS));
0000ae  ea414104          ORR      r1,r1,r4,LSL #16
;;;591                 CPU_REG_NVIC_SHPRI3  = temp;
0000b2  6039              STR      r1,[r7,#0]
;;;592                 CPU_CRITICAL_EXIT();
0000b4  e8bd41f0          POP      {r4-r8,lr}
0000b8  f7ffbffe          B.W      CPU_SR_Restore
;;;593                 break;
;;;594    
;;;595            case CPU_INT_SYSTICK:                                   /* SysTick.                                             */
;;;596                 CPU_CRITICAL_ENTER();
0000bc  f7fffffe          BL       CPU_SR_Save
;;;597                 temp                 = CPU_REG_NVIC_SHPRI3;
0000c0  6839              LDR      r1,[r7,#0]
;;;598                 temp                &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
0000c2  f021417f          BIC      r1,r1,#0xff000000
;;;599                 temp                |=  (prio                       << (3 * DEF_OCTET_NBR_BITS));
0000c6  ea416104          ORR      r1,r1,r4,LSL #24
;;;600                 CPU_REG_NVIC_SHPRI3  = temp;
0000ca  6039              STR      r1,[r7,#0]
;;;601                 CPU_CRITICAL_EXIT();
0000cc  e8bd41f0          POP      {r4-r8,lr}
0000d0  f7ffbffe          B.W      CPU_SR_Restore
                  |L7.212|
;;;602                 break;
;;;603    
;;;604    
;;;605                                                                    /* ---------------- EXTERNAL INTERRUPT ---------------- */
;;;606            default:
;;;607                pos_max = CPU_INT_SRC_POS_MAX;
0000d4  f04f20e0          MOV      r0,#0xe000e000
0000d8  6840              LDR      r0,[r0,#4]
0000da  1c40              ADDS     r0,r0,#1
0000dc  2110              MOVS     r1,#0x10
0000de  eb011040          ADD      r0,r1,r0,LSL #5
0000e2  b2c0              UXTB     r0,r0
;;;608                if (pos < pos_max) {                                /* See Note #3.                                         */
0000e4  4285              CMP      r5,r0
0000e6  d21b              BCS      |L7.288|
;;;609                     group                    = (pos - 16) / 4;
0000e8  3d10              SUBS     r5,r5,#0x10
0000ea  17e8              ASRS     r0,r5,#31
0000ec  eb057090          ADD      r0,r5,r0,LSR #30
0000f0  f3c00687          UBFX     r6,r0,#2,#8
;;;610                     nbr                      = (pos - 16) % 4;
0000f4  f0200003          BIC      r0,r0,#3
0000f8  1a2d              SUBS     r5,r5,r0
;;;611    
;;;612                     CPU_CRITICAL_ENTER();
0000fa  f7fffffe          BL       CPU_SR_Save
;;;613                     temp                     = CPU_REG_NVIC_PRIO(group);
0000fe  00b1              LSLS     r1,r6,#2
000100  f10121e0          ADD      r1,r1,#0xe000e000
000104  f8d13400          LDR      r3,[r1,#0x400]
;;;614                     temp                    &= ~(DEF_OCTET_MASK << (nbr * DEF_OCTET_NBR_BITS));
000108  00ea              LSLS     r2,r5,#3
00010a  25ff              MOVS     r5,#0xff
00010c  4095              LSLS     r5,r5,r2
00010e  43ab              BICS     r3,r3,r5
;;;615                     temp                    |=  (prio           << (nbr * DEF_OCTET_NBR_BITS));
000110  4094              LSLS     r4,r4,r2
000112  431c              ORRS     r4,r4,r3
;;;616                     CPU_REG_NVIC_PRIO(group) = temp;
000114  f8c14400          STR      r4,[r1,#0x400]
;;;617                     CPU_CRITICAL_EXIT();
000118  e8bd41f0          POP      {r4-r8,lr}
00011c  f7ffbffe          B.W      CPU_SR_Restore
                  |L7.288|
;;;618                 }
;;;619                 break;
;;;620        }
;;;621    }
000120  e8bd81f0          POP      {r4-r8,pc}
;;;622    
                          ENDP

                  |L7.292|
                          DCD      0xe000ed18