stm32f4xx_spi.txt 50.4 KB

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; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\flash\obj\stm32f4xx_spi.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\stm32f4xx_spi.d --cpu=Cortex-M4.fp --apcs=interwork -O1 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Include -I..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\uCOS-III\uC-CPU -I..\..\uCOS-III\uC-LIB -I..\..\uCOS-III\uCOS-III\Ports -I..\..\uCOS-III\uCOS-III\Source -I..\..\uCOS-III\uC-CPU\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uC-LIB\Ports\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uCOS-III\Ports\ARM-Cortex-M4\Generic\RealView -I..\..\User -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\libapp -I..\..\RL-ARM\Config -I..\..\RL-ARM\Driver -I..\..\RL-ARM\RL-RTX\inc -I..\..\User\bsp\BSP -I..\..\RL-ARM\RL-CAN -I..\..\Libraries\DSP_LIB\Include -I..\..\MODBUS\modbus\rtu -I..\..\MODBUS\BARE\port -I..\..\MODBUS\modbus\include -I..\..\User\bsp\BSP -I..\..\PLC -I..\..\Avoid -I..\..\User\parameter -I..\..\User\LaserMotionCtr -I..\..\User\W5100S -I..\..\User\bsp -I..\..\User\CHASSIS -I..\..\User\CONTROLFUNCTION -I..\..\User\DATAUPDATE -I..\..\User\HARAWARE -I..\..\User\MOTORDRIVER -I..\..\User\NAVAGATION -I..\..\User\PLATFORM -I..\..\User\SENSOR -I.\RTE\_Flash -IC:\Users\YDJ\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include -IC:\Users\YDJ\AppData\Local\Arm\Packs\Keil\STM32F4xx_DFP\2.13.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include -D__UVISION_VERSION=527 -D_RTE_ -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -D__RTX -D__FPU_USED=1 --omf_browse=.\flash\obj\stm32f4xx_spi.crf ..\..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_spi.c]
                          THUMB

                          AREA ||i.I2S_Cmd||, CODE, READONLY, ALIGN=1

                  I2S_Cmd PROC
;;;568      */
;;;569    void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;570    {
000002  d004              BEQ      |L1.14|
;;;571      /* Check the parameters */
;;;572      assert_param(IS_SPI_23_PERIPH_EXT(SPIx));
;;;573      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;574
;;;575      if (NewState != DISABLE)
;;;576      {
;;;577        /* Enable the selected SPI peripheral (in I2S mode) */
;;;578        SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
000004  8b81              LDRH     r1,[r0,#0x1c]
000006  f4416180          ORR      r1,r1,#0x400
00000a  8381              STRH     r1,[r0,#0x1c]
;;;579      }
;;;580      else
;;;581      {
;;;582        /* Disable the selected SPI peripheral in I2S mode */
;;;583        SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
;;;584      }
;;;585    }
00000c  4770              BX       lr
                  |L1.14|
00000e  8b81              LDRH     r1,[r0,#0x1c]         ;583
000010  f4216180          BIC      r1,r1,#0x400          ;583
000014  8381              STRH     r1,[r0,#0x1c]         ;583
000016  4770              BX       lr
;;;586
                          ENDP


                          AREA ||i.I2S_FullDuplexConfig||, CODE, READONLY, ALIGN=1

                  I2S_FullDuplexConfig PROC
;;;733      */
;;;734    void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct)
000000  b530              PUSH     {r4,r5,lr}
;;;735    {
;;;736      uint16_t tmpreg = 0, tmp = 0;
000002  2300              MOVS     r3,#0
;;;737
;;;738      /* Check the I2S parameters */
;;;739      assert_param(IS_I2S_EXT_PERIPH(I2Sxext));
;;;740      assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
;;;741      assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
;;;742      assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
;;;743      assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
;;;744
;;;745    /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
;;;746      /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
;;;747      I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK;
000004  8b82              LDRH     r2,[r0,#0x1c]
000006  f24f0440          MOV      r4,#0xf040
00000a  4022              ANDS     r2,r2,r4
00000c  8382              STRH     r2,[r0,#0x1c]
;;;748      I2Sxext->I2SPR = 0x0002;
00000e  2202              MOVS     r2,#2
000010  8402              STRH     r2,[r0,#0x20]
;;;749
;;;750      /* Get the I2SCFGR register value */
;;;751      tmpreg = I2Sxext->I2SCFGR;
000012  8b84              LDRH     r4,[r0,#0x1c]
;;;752
;;;753      /* Get the mode to be configured for the extended I2S */
;;;754      if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx))
000014  880a              LDRH     r2,[r1,#0]
;;;755      {
;;;756        tmp = I2S_Mode_SlaveRx;
000016  f44f7580          MOV      r5,#0x100
00001a  f5b27f00          CMP      r2,#0x200             ;754
00001e  d000              BEQ      |L2.34|
000020  b902              CBNZ     r2,|L2.36|
                  |L2.34|
000022  462b              MOV      r3,r5
                  |L2.36|
;;;757      }
;;;758      else
;;;759      {
;;;760        if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx))
;;;761        {
;;;762          tmp = I2S_Mode_SlaveTx;
;;;763        }
;;;764      }
;;;765
;;;766
;;;767      /* Configure the I2S with the SPI_InitStruct values */
;;;768      tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
000024  884a              LDRH     r2,[r1,#2]
000026  888d              LDRH     r5,[r1,#4]
000028  8989              LDRH     r1,[r1,#0xc]
00002a  432a              ORRS     r2,r2,r5
00002c  4319              ORRS     r1,r1,r3
00002e  430a              ORRS     r2,r2,r1
000030  4322              ORRS     r2,r2,r4
000032  f4426100          ORR      r1,r2,#0x800
;;;769                      (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
;;;770                      (uint16_t)I2S_InitStruct->I2S_CPOL))));
;;;771
;;;772      /* Write to SPIx I2SCFGR */
;;;773      I2Sxext->I2SCFGR = tmpreg;
000036  8381              STRH     r1,[r0,#0x1c]
;;;774    }
000038  bd30              POP      {r4,r5,pc}
;;;775
                          ENDP


                          AREA ||i.I2S_Init||, CODE, READONLY, ALIGN=2

                  I2S_Init PROC
;;;347      */
;;;348    void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
000000  b5f0              PUSH     {r4-r7,lr}
;;;349    {
;;;350      uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
000002  2202              MOVS     r2,#2
000004  2300              MOVS     r3,#0
000006  2401              MOVS     r4,#1
;;;351      uint32_t tmp = 0, i2sclk = 0;
;;;352    #ifndef I2S_EXTERNAL_CLOCK_VAL
;;;353      uint32_t pllm = 0, plln = 0, pllr = 0;
;;;354    #endif /* I2S_EXTERNAL_CLOCK_VAL */
;;;355
;;;356      /* Check the I2S parameters */
;;;357      assert_param(IS_SPI_23_PERIPH(SPIx));
;;;358      assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
;;;359      assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
;;;360      assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
;;;361      assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
;;;362      assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
;;;363      assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
;;;364
;;;365    /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
;;;366      /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
;;;367      SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK;
000008  8b85              LDRH     r5,[r0,#0x1c]
00000a  f24f0640          MOV      r6,#0xf040
00000e  4035              ANDS     r5,r5,r6
000010  8385              STRH     r5,[r0,#0x1c]
;;;368      SPIx->I2SPR = 0x0002;
000012  2502              MOVS     r5,#2
000014  8405              STRH     r5,[r0,#0x20]
;;;369
;;;370      /* Get the I2SCFGR register value */
;;;371      tmpreg = SPIx->I2SCFGR;
000016  8b86              LDRH     r6,[r0,#0x1c]
;;;372
;;;373      /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
;;;374      if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
000018  688d              LDR      r5,[r1,#8]
00001a  2d02              CMP      r5,#2
00001c  d042              BEQ      |L3.164|
;;;375      {
;;;376        i2sodd = (uint16_t)0;
;;;377        i2sdiv = (uint16_t)2;
;;;378      }
;;;379      /* If the requested audio frequency is not the default, compute the prescaler */
;;;380      else
;;;381      {
;;;382        /* Check the frame length (For the Prescaler computing) *******************/
;;;383        if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
00001e  888a              LDRH     r2,[r1,#4]
000020  b102              CBZ      r2,|L3.36|
;;;384        {
;;;385          /* Packet length is 16 bits */
;;;386          packetlength = 1;
;;;387        }
;;;388        else
;;;389        {
;;;390          /* Packet length is 32 bits */
;;;391          packetlength = 2;
000022  2402              MOVS     r4,#2
                  |L3.36|
;;;392        }
;;;393
;;;394        /* Get I2S source Clock frequency  ****************************************/
;;;395
;;;396        /* If an external I2S clock has to be used, this define should be set
;;;397           in the project configuration or in the stm32f4xx_conf.h file */
;;;398      #ifdef I2S_EXTERNAL_CLOCK_VAL
;;;399        /* Set external clock as I2S clock source */
;;;400        if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0)
;;;401        {
;;;402          RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
;;;403        }
;;;404
;;;405        /* Set the I2S clock to the external clock  value */
;;;406        i2sclk = I2S_EXTERNAL_CLOCK_VAL;
;;;407
;;;408      #else /* There is no define for External I2S clock source */
;;;409        /* Set PLLI2S as I2S clock source */
;;;410        if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0)
000024  4a2f              LDR      r2,|L3.228|
000026  6813              LDR      r3,[r2,#0]
000028  021b              LSLS     r3,r3,#8
00002a  d503              BPL      |L3.52|
;;;411        {
;;;412          RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
00002c  6813              LDR      r3,[r2,#0]
00002e  f4230300          BIC      r3,r3,#0x800000
000032  6013              STR      r3,[r2,#0]
                  |L3.52|
;;;413        }
;;;414
;;;415        /* Get the PLLI2SN value */
;;;416        plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \
000034  4a2b              LDR      r2,|L3.228|
000036  327c              ADDS     r2,r2,#0x7c
000038  6813              LDR      r3,[r2,#0]
00003a  f3c31388          UBFX     r3,r3,#6,#9
;;;417                          (RCC_PLLI2SCFGR_PLLI2SN >> 6));
;;;418
;;;419        /* Get the PLLI2SR value */
;;;420        pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \
00003e  6812              LDR      r2,[r2,#0]
000040  f3c27502          UBFX     r5,r2,#28,#3
;;;421                          (RCC_PLLI2SCFGR_PLLI2SR >> 28));
;;;422
;;;423        /* Get the PLLM value */
;;;424        pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
000044  4f27              LDR      r7,|L3.228|
000046  1f3f              SUBS     r7,r7,#4
000048  683a              LDR      r2,[r7,#0]
00004a  f002023f          AND      r2,r2,#0x3f
;;;425
;;;426        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)
00004e  683f              LDR      r7,[r7,#0]
000050  027f              LSLS     r7,r7,#9
000052  d506              BPL      |L3.98|
;;;427        {
;;;428          /* Get the I2S source clock value */
;;;429          i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr);
000054  4f24              LDR      r7,|L3.232|
000056  fbb7f2f2          UDIV     r2,r7,r2
00005a  435a              MULS     r2,r3,r2
00005c  fbb2f2f5          UDIV     r2,r2,r5
000060  e005              B        |L3.110|
                  |L3.98|
;;;430        }
;;;431        else
;;;432        { /* Get the I2S source clock value */
;;;433          i2sclk = (uint32_t)(((HSI_VALUE / pllm) * plln) / pllr);
000062  4f22              LDR      r7,|L3.236|
000064  fbb7f2f2          UDIV     r2,r7,r2
000068  435a              MULS     r2,r3,r2
00006a  fbb2f2f5          UDIV     r2,r2,r5
                  |L3.110|
;;;434        }
;;;435      #endif /* I2S_EXTERNAL_CLOCK_VAL */
;;;436
;;;437        /* Compute the Real divider depending on the MCLK output state, with a floating point */
;;;438        if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
00006e  88cb              LDRH     r3,[r1,#6]
000070  f5b37f00          CMP      r3,#0x200
000074  d02b              BEQ      |L3.206|
;;;439        {
;;;440          /* MCLK output is enabled */
;;;441          tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
;;;442        }
;;;443        else
;;;444        {
;;;445          /* MCLK output is disabled */
;;;446          tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
000076  0163              LSLS     r3,r4,#5
000078  fbb2f2f3          UDIV     r2,r2,r3
00007c  eb020282          ADD      r2,r2,r2,LSL #2
000080  688b              LDR      r3,[r1,#8]
000082  0052              LSLS     r2,r2,#1
000084  fbb2f2f3          UDIV     r2,r2,r3
000088  1d52              ADDS     r2,r2,#5
00008a  b292              UXTH     r2,r2
                  |L3.140|
;;;447        }
;;;448
;;;449        /* Remove the flatting point */
;;;450        tmp = tmp / 10;
00008c  230a              MOVS     r3,#0xa
00008e  fbb2f2f3          UDIV     r2,r2,r3
;;;451
;;;452        /* Check the parity of the divider */
;;;453        i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
000092  f0020301          AND      r3,r2,#1
;;;454
;;;455        /* Compute the i2sdiv prescaler */
;;;456        i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
000096  1ad2              SUBS     r2,r2,r3
000098  f3c2024f          UBFX     r2,r2,#1,#16
;;;457
;;;458        /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
;;;459        i2sodd = (uint16_t) (i2sodd << 8);
00009c  f64f74ff          MOV      r4,#0xffff
0000a0  ea042303          AND      r3,r4,r3,LSL #8
                  |L3.164|
;;;460      }
;;;461
;;;462      /* Test if the divider is 1 or 0 or greater than 0xFF */
;;;463      if ((i2sdiv < 2) || (i2sdiv > 0xFF))
0000a4  1e94              SUBS     r4,r2,#2
0000a6  2cfe              CMP      r4,#0xfe
0000a8  d301              BCC      |L3.174|
;;;464      {
;;;465        /* Set the default values */
;;;466        i2sdiv = 2;
0000aa  2202              MOVS     r2,#2
;;;467        i2sodd = 0;
0000ac  2300              MOVS     r3,#0
                  |L3.174|
;;;468      }
;;;469
;;;470      /* Write to SPIx I2SPR register the computed value */
;;;471      SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
0000ae  88cc              LDRH     r4,[r1,#6]
0000b0  431a              ORRS     r2,r2,r3
0000b2  4314              ORRS     r4,r4,r2
0000b4  8404              STRH     r4,[r0,#0x20]
;;;472
;;;473      /* Configure the I2S with the SPI_InitStruct values */
;;;474      tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
0000b6  880a              LDRH     r2,[r1,#0]
0000b8  884b              LDRH     r3,[r1,#2]
0000ba  431a              ORRS     r2,r2,r3
0000bc  888b              LDRH     r3,[r1,#4]
0000be  8989              LDRH     r1,[r1,#0xc]
0000c0  430b              ORRS     r3,r3,r1
0000c2  431a              ORRS     r2,r2,r3
0000c4  4332              ORRS     r2,r2,r6
0000c6  f4426100          ORR      r1,r2,#0x800
;;;475                      (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
;;;476                      (uint16_t)I2S_InitStruct->I2S_CPOL))));
;;;477
;;;478      /* Write to SPIx I2SCFGR */
;;;479      SPIx->I2SCFGR = tmpreg;
0000ca  8381              STRH     r1,[r0,#0x1c]
;;;480    }
0000cc  bdf0              POP      {r4-r7,pc}
                  |L3.206|
0000ce  0a12              LSRS     r2,r2,#8              ;441
0000d0  eb020282          ADD      r2,r2,r2,LSL #2       ;441
0000d4  688b              LDR      r3,[r1,#8]            ;441
0000d6  0052              LSLS     r2,r2,#1              ;441
0000d8  fbb2f2f3          UDIV     r2,r2,r3              ;441
0000dc  1d52              ADDS     r2,r2,#5              ;441
0000de  b292              UXTH     r2,r2                 ;441
0000e0  e7d4              B        |L3.140|
;;;481
                          ENDP

0000e2  0000              DCW      0x0000
                  |L3.228|
                          DCD      0x40023808
                  |L3.232|
                          DCD      0x007a1200
                  |L3.236|
                          DCD      0x00f42400

                          AREA ||i.I2S_StructInit||, CODE, READONLY, ALIGN=1

                  I2S_StructInit PROC
;;;514      */
;;;515    void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
000000  2100              MOVS     r1,#0
;;;516    {
;;;517    /*--------------- Reset I2S init structure parameters values -----------------*/
;;;518      /* Initialize the I2S_Mode member */
;;;519      I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
000002  8001              STRH     r1,[r0,#0]
;;;520
;;;521      /* Initialize the I2S_Standard member */
;;;522      I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
000004  8041              STRH     r1,[r0,#2]
;;;523
;;;524      /* Initialize the I2S_DataFormat member */
;;;525      I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
000006  8081              STRH     r1,[r0,#4]
;;;526
;;;527      /* Initialize the I2S_MCLKOutput member */
;;;528      I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
000008  80c1              STRH     r1,[r0,#6]
;;;529
;;;530      /* Initialize the I2S_AudioFreq member */
;;;531      I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
00000a  2202              MOVS     r2,#2
00000c  6082              STR      r2,[r0,#8]
;;;532
;;;533      /* Initialize the I2S_CPOL member */
;;;534      I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
00000e  8181              STRH     r1,[r0,#0xc]
;;;535    }
000010  4770              BX       lr
;;;536
                          ENDP


                          AREA ||i.SPI_BiDirectionalLineConfig||, CODE, READONLY, ALIGN=1

                  SPI_BiDirectionalLineConfig PROC
;;;615      */
;;;616    void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
000000  f5b14f80          CMP      r1,#0x4000
;;;617    {
000004  d004              BEQ      |L5.16|
;;;618      /* Check the parameters */
;;;619      assert_param(IS_SPI_ALL_PERIPH(SPIx));
;;;620      assert_param(IS_SPI_DIRECTION(SPI_Direction));
;;;621      if (SPI_Direction == SPI_Direction_Tx)
;;;622      {
;;;623        /* Set the Tx only mode */
;;;624        SPIx->CR1 |= SPI_Direction_Tx;
;;;625      }
;;;626      else
;;;627      {
;;;628        /* Set the Rx only mode */
;;;629        SPIx->CR1 &= SPI_Direction_Rx;
000006  8801              LDRH     r1,[r0,#0]
000008  f4214180          BIC      r1,r1,#0x4000
00000c  8001              STRH     r1,[r0,#0]
;;;630      }
;;;631    }
00000e  4770              BX       lr
                  |L5.16|
000010  8801              LDRH     r1,[r0,#0]            ;624
000012  f4414180          ORR      r1,r1,#0x4000         ;624
000016  8001              STRH     r1,[r0,#0]            ;624
000018  4770              BX       lr
;;;632
                          ENDP


                          AREA ||i.SPI_CalculateCRC||, CODE, READONLY, ALIGN=1

                  SPI_CalculateCRC PROC
;;;913      */
;;;914    void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;915    {
000002  d004              BEQ      |L6.14|
;;;916      /* Check the parameters */
;;;917      assert_param(IS_SPI_ALL_PERIPH(SPIx));
;;;918      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;919      if (NewState != DISABLE)
;;;920      {
;;;921        /* Enable the selected SPI CRC calculation */
;;;922        SPIx->CR1 |= SPI_CR1_CRCEN;
000004  8801              LDRH     r1,[r0,#0]
000006  f4415100          ORR      r1,r1,#0x2000
00000a  8001              STRH     r1,[r0,#0]
;;;923      }
;;;924      else
;;;925      {
;;;926        /* Disable the selected SPI CRC calculation */
;;;927        SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
;;;928      }
;;;929    }
00000c  4770              BX       lr
                  |L6.14|
00000e  8801              LDRH     r1,[r0,#0]            ;927
000010  f4215100          BIC      r1,r1,#0x2000         ;927
000014  8001              STRH     r1,[r0,#0]            ;927
000016  4770              BX       lr
;;;930
                          ENDP


                          AREA ||i.SPI_Cmd||, CODE, READONLY, ALIGN=1

                  SPI_Cmd PROC
;;;543      */
;;;544    void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;545    {
000002  d004              BEQ      |L7.14|
;;;546      /* Check the parameters */
;;;547      assert_param(IS_SPI_ALL_PERIPH(SPIx));
;;;548      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;549      if (NewState != DISABLE)
;;;550      {
;;;551        /* Enable the selected SPI peripheral */
;;;552        SPIx->CR1 |= SPI_CR1_SPE;
000004  8801              LDRH     r1,[r0,#0]
000006  f0410140          ORR      r1,r1,#0x40
00000a  8001              STRH     r1,[r0,#0]
;;;553      }
;;;554      else
;;;555      {
;;;556        /* Disable the selected SPI peripheral */
;;;557        SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
;;;558      }
;;;559    }
00000c  4770              BX       lr
                  |L7.14|
00000e  8801              LDRH     r1,[r0,#0]            ;557
000010  f0210140          BIC      r1,r1,#0x40           ;557
000014  8001              STRH     r1,[r0,#0]            ;557
000016  4770              BX       lr
;;;560
                          ENDP


                          AREA ||i.SPI_DataSizeConfig||, CODE, READONLY, ALIGN=1

                  SPI_DataSizeConfig PROC
;;;595      */
;;;596    void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
000000  8802              LDRH     r2,[r0,#0]
;;;597    {
;;;598      /* Check the parameters */
;;;599      assert_param(IS_SPI_ALL_PERIPH(SPIx));
;;;600      assert_param(IS_SPI_DATASIZE(SPI_DataSize));
;;;601      /* Clear DFF bit */
;;;602      SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
000002  f4226200          BIC      r2,r2,#0x800
000006  8002              STRH     r2,[r0,#0]
;;;603      /* Set new DFF bit value */
;;;604      SPIx->CR1 |= SPI_DataSize;
000008  8802              LDRH     r2,[r0,#0]
00000a  430a              ORRS     r2,r2,r1
00000c  8002              STRH     r2,[r0,#0]
;;;605    }
00000e  4770              BX       lr
;;;606
                          ENDP


                          AREA ||i.SPI_GetCRC||, CODE, READONLY, ALIGN=1

                  SPI_GetCRC PROC
;;;953      */
;;;954    uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
000000  2901              CMP      r1,#1
;;;955    {
000002  d001              BEQ      |L9.8|
;;;956      uint16_t crcreg = 0;
;;;957      /* Check the parameters */
;;;958      assert_param(IS_SPI_ALL_PERIPH(SPIx));
;;;959      assert_param(IS_SPI_CRC(SPI_CRC));
;;;960      if (SPI_CRC != SPI_CRC_Rx)
;;;961      {
;;;962        /* Get the Tx CRC register */
;;;963        crcreg = SPIx->TXCRCR;
000004  8b00              LDRH     r0,[r0,#0x18]
;;;964      }
;;;965      else
;;;966      {
;;;967        /* Get the Rx CRC register */
;;;968        crcreg = SPIx->RXCRCR;
;;;969      }
;;;970      /* Return the selected CRC register */
;;;971      return crcreg;
;;;972    }
000006  4770              BX       lr
                  |L9.8|
000008  8a80              LDRH     r0,[r0,#0x14]         ;968
00000a  4770              BX       lr
;;;973
                          ENDP


                          AREA ||i.SPI_GetCRCPolynomial||, CODE, READONLY, ALIGN=1

                  SPI_GetCRCPolynomial PROC
;;;978      */
;;;979    uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
000000  8a00              LDRH     r0,[r0,#0x10]
;;;980    {
;;;981      /* Check the parameters */
;;;982      assert_param(IS_SPI_ALL_PERIPH(SPIx));
;;;983
;;;984      /* Return the CRC polynomial register */
;;;985      return SPIx->CRCPR;
;;;986    }
000002  4770              BX       lr
;;;987
                          ENDP


                          AREA ||i.SPI_I2S_ClearFlag||, CODE, READONLY, ALIGN=1

                  SPI_I2S_ClearFlag PROC
;;;1208     */
;;;1209   void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
000000  43c9              MVNS     r1,r1
;;;1210   {
;;;1211     /* Check the parameters */
;;;1212     assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
;;;1213     assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
;;;1214
;;;1215     /* Clear the selected SPI CRC Error (CRCERR) flag */
;;;1216     SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
000002  8101              STRH     r1,[r0,#8]
;;;1217   }
000004  4770              BX       lr
;;;1218
                          ENDP


                          AREA ||i.SPI_I2S_ClearITPendingBit||, CODE, READONLY, ALIGN=1

                  SPI_I2S_ClearITPendingBit PROC
;;;1288     */
;;;1289   void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
000000  f001020f          AND      r2,r1,#0xf
;;;1290   {
;;;1291     uint16_t itpos = 0;
;;;1292     /* Check the parameters */
;;;1293     assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
;;;1294     assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
;;;1295
;;;1296     /* Get the SPI_I2S IT index */
;;;1297     itpos = 0x01 << (SPI_I2S_IT & 0x0F);
000004  2101              MOVS     r1,#1
000006  4091              LSLS     r1,r1,r2
;;;1298
;;;1299     /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
;;;1300     SPIx->SR = (uint16_t)~itpos;
000008  43c9              MVNS     r1,r1
00000a  8101              STRH     r1,[r0,#8]
;;;1301   }
00000c  4770              BX       lr
;;;1302
                          ENDP


                          AREA ||i.SPI_I2S_DMACmd||, CODE, READONLY, ALIGN=1

                  SPI_I2S_DMACmd PROC
;;;1015     */
;;;1016   void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
000000  2a00              CMP      r2,#0
;;;1017   {
000002  d003              BEQ      |L13.12|
;;;1018     /* Check the parameters */
;;;1019     assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
;;;1020     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1021     assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
;;;1022
;;;1023     if (NewState != DISABLE)
;;;1024     {
;;;1025       /* Enable the selected SPI DMA requests */
;;;1026       SPIx->CR2 |= SPI_I2S_DMAReq;
000004  8882              LDRH     r2,[r0,#4]
000006  430a              ORRS     r2,r2,r1
000008  8082              STRH     r2,[r0,#4]
;;;1027     }
;;;1028     else
;;;1029     {
;;;1030       /* Disable the selected SPI DMA requests */
;;;1031       SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
;;;1032     }
;;;1033   }
00000a  4770              BX       lr
                  |L13.12|
00000c  8882              LDRH     r2,[r0,#4]            ;1031
00000e  438a              BICS     r2,r2,r1              ;1031
000010  8082              STRH     r2,[r0,#4]            ;1031
000012  4770              BX       lr
;;;1034
                          ENDP


                          AREA ||i.SPI_I2S_DeInit||, CODE, READONLY, ALIGN=2

                  SPI_I2S_DeInit PROC
;;;223      */
;;;224    void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
000000  b510              PUSH     {r4,lr}
;;;225    {
;;;226      /* Check the parameters */
;;;227      assert_param(IS_SPI_ALL_PERIPH(SPIx));
;;;228
;;;229      if (SPIx == SPI1)
000002  492a              LDR      r1,|L14.172|
000004  4288              CMP      r0,r1
000006  d10a              BNE      |L14.30|
;;;230      {
;;;231        /* Enable SPI1 reset state */
;;;232        RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
000008  1484              ASRS     r4,r0,#18
00000a  2101              MOVS     r1,#1
00000c  4620              MOV      r0,r4
00000e  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;233        /* Release SPI1 from reset state */
;;;234        RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
000012  4620              MOV      r0,r4
000014  e8bd4010          POP      {r4,lr}
000018  2100              MOVS     r1,#0
00001a  f7ffbffe          B.W      RCC_APB2PeriphResetCmd
                  |L14.30|
;;;235      }
;;;236      else if (SPIx == SPI2)
00001e  4924              LDR      r1,|L14.176|
000020  4288              CMP      r0,r1
000022  d10a              BNE      |L14.58|
;;;237      {
;;;238        /* Enable SPI2 reset state */
;;;239        RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
000024  1404              ASRS     r4,r0,#16
000026  2101              MOVS     r1,#1
000028  4620              MOV      r0,r4
00002a  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;240        /* Release SPI2 from reset state */
;;;241        RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
00002e  4620              MOV      r0,r4
000030  e8bd4010          POP      {r4,lr}
000034  2100              MOVS     r1,#0
000036  f7ffbffe          B.W      RCC_APB1PeriphResetCmd
                  |L14.58|
;;;242      }
;;;243      else if (SPIx == SPI3)
00003a  491e              LDR      r1,|L14.180|
00003c  4288              CMP      r0,r1
00003e  d10a              BNE      |L14.86|
;;;244      {
;;;245        /* Enable SPI3 reset state */
;;;246        RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
000040  13c4              ASRS     r4,r0,#15
000042  2101              MOVS     r1,#1
000044  4620              MOV      r0,r4
000046  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;247        /* Release SPI3 from reset state */
;;;248        RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
00004a  4620              MOV      r0,r4
00004c  e8bd4010          POP      {r4,lr}
000050  2100              MOVS     r1,#0
000052  f7ffbffe          B.W      RCC_APB1PeriphResetCmd
                  |L14.86|
;;;249      }
;;;250      else if (SPIx == SPI4)
000056  4918              LDR      r1,|L14.184|
000058  4288              CMP      r0,r1
00005a  d10a              BNE      |L14.114|
;;;251      {
;;;252        /* Enable SPI4 reset state */
;;;253        RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, ENABLE);
00005c  1444              ASRS     r4,r0,#17
00005e  2101              MOVS     r1,#1
000060  4620              MOV      r0,r4
000062  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;254        /* Release SPI4 from reset state */
;;;255        RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, DISABLE);
000066  4620              MOV      r0,r4
000068  e8bd4010          POP      {r4,lr}
00006c  2100              MOVS     r1,#0
00006e  f7ffbffe          B.W      RCC_APB2PeriphResetCmd
                  |L14.114|
;;;256      }
;;;257      else if (SPIx == SPI5)
000072  4912              LDR      r1,|L14.188|
000074  4288              CMP      r0,r1
000076  d10a              BNE      |L14.142|
;;;258      {
;;;259        /* Enable SPI5 reset state */
;;;260        RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, ENABLE);
000078  2101              MOVS     r1,#1
00007a  050c              LSLS     r4,r1,#20
00007c  4620              MOV      r0,r4
00007e  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;261        /* Release SPI5 from reset state */
;;;262        RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, DISABLE);
000082  4620              MOV      r0,r4
000084  e8bd4010          POP      {r4,lr}
000088  2100              MOVS     r1,#0
00008a  f7ffbffe          B.W      RCC_APB2PeriphResetCmd
                  |L14.142|
;;;263      }
;;;264      else
;;;265      {
;;;266        if (SPIx == SPI6)
00008e  490c              LDR      r1,|L14.192|
000090  4288              CMP      r0,r1
000092  d10a              BNE      |L14.170|
;;;267        {
;;;268          /* Enable SPI6 reset state */
;;;269          RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, ENABLE);
000094  2101              MOVS     r1,#1
000096  054c              LSLS     r4,r1,#21
000098  4620              MOV      r0,r4
00009a  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;270          /* Release SPI6 from reset state */
;;;271          RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, DISABLE);
00009e  4620              MOV      r0,r4
0000a0  e8bd4010          POP      {r4,lr}
0000a4  2100              MOVS     r1,#0
0000a6  f7ffbffe          B.W      RCC_APB2PeriphResetCmd
                  |L14.170|
;;;272        }
;;;273      }
;;;274    }
0000aa  bd10              POP      {r4,pc}
;;;275
                          ENDP

                  |L14.172|
                          DCD      0x40013000
                  |L14.176|
                          DCD      0x40003800
                  |L14.180|
                          DCD      0x40003c00
                  |L14.184|
                          DCD      0x40013400
                  |L14.188|
                          DCD      0x40015000
                  |L14.192|
                          DCD      0x40015400

                          AREA ||i.SPI_I2S_GetFlagStatus||, CODE, READONLY, ALIGN=1

                  SPI_I2S_GetFlagStatus PROC
;;;1167     */
;;;1168   FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
000000  4602              MOV      r2,r0
;;;1169   {
;;;1170     FlagStatus bitstatus = RESET;
000002  2000              MOVS     r0,#0
;;;1171     /* Check the parameters */
;;;1172     assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
;;;1173     assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
;;;1174
;;;1175     /* Check the status of the specified SPI flag */
;;;1176     if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
000004  8912              LDRH     r2,[r2,#8]
000006  420a              TST      r2,r1
000008  d000              BEQ      |L15.12|
;;;1177     {
;;;1178       /* SPI_I2S_FLAG is set */
;;;1179       bitstatus = SET;
00000a  2001              MOVS     r0,#1
                  |L15.12|
;;;1180     }
;;;1181     else
;;;1182     {
;;;1183       /* SPI_I2S_FLAG is reset */
;;;1184       bitstatus = RESET;
;;;1185     }
;;;1186     /* Return the SPI_I2S_FLAG status */
;;;1187     return  bitstatus;
;;;1188   }
00000c  4770              BX       lr
;;;1189
                          ENDP


                          AREA ||i.SPI_I2S_GetITStatus||, CODE, READONLY, ALIGN=1

                  SPI_I2S_GetITStatus PROC
;;;1233     */
;;;1234   ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
000000  b530              PUSH     {r4,r5,lr}
;;;1235   {
000002  4602              MOV      r2,r0
;;;1236     ITStatus bitstatus = RESET;
000004  2000              MOVS     r0,#0
;;;1237     uint16_t itpos = 0, itmask = 0, enablestatus = 0;
;;;1238
;;;1239     /* Check the parameters */
;;;1240     assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
;;;1241     assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
;;;1242
;;;1243     /* Get the SPI_I2S_IT index */
;;;1244     itpos = 0x01 << (SPI_I2S_IT & 0x0F);
000006  f001030f          AND      r3,r1,#0xf
00000a  2501              MOVS     r5,#1
00000c  fa05f403          LSL      r4,r5,r3
000010  b2a3              UXTH     r3,r4
;;;1245
;;;1246     /* Get the SPI_I2S_IT IT mask */
;;;1247     itmask = SPI_I2S_IT >> 4;
000012  0909              LSRS     r1,r1,#4
;;;1248
;;;1249     /* Set the IT mask */
;;;1250     itmask = 0x01 << itmask;
000014  fa05f401          LSL      r4,r5,r1
000018  b2a4              UXTH     r4,r4
;;;1251
;;;1252     /* Get the SPI_I2S_IT enable bit status */
;;;1253     enablestatus = (SPIx->CR2 & itmask) ;
00001a  8891              LDRH     r1,[r2,#4]
00001c  4021              ANDS     r1,r1,r4
;;;1254
;;;1255     /* Check the status of the specified SPI interrupt */
;;;1256     if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
00001e  8912              LDRH     r2,[r2,#8]
000020  421a              TST      r2,r3
000022  d002              BEQ      |L16.42|
000024  2900              CMP      r1,#0
000026  d000              BEQ      |L16.42|
;;;1257     {
;;;1258       /* SPI_I2S_IT is set */
;;;1259       bitstatus = SET;
000028  2001              MOVS     r0,#1
                  |L16.42|
;;;1260     }
;;;1261     else
;;;1262     {
;;;1263       /* SPI_I2S_IT is reset */
;;;1264       bitstatus = RESET;
;;;1265     }
;;;1266     /* Return the SPI_I2S_IT status */
;;;1267     return bitstatus;
;;;1268   }
00002a  bd30              POP      {r4,r5,pc}
;;;1269
                          ENDP


                          AREA ||i.SPI_I2S_ITConfig||, CODE, READONLY, ALIGN=1

                  SPI_I2S_ITConfig PROC
;;;1123     */
;;;1124   void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
000000  0909              LSRS     r1,r1,#4
;;;1125   {
;;;1126     uint16_t itpos = 0, itmask = 0 ;
;;;1127
;;;1128     /* Check the parameters */
;;;1129     assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
;;;1130     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1131     assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
;;;1132
;;;1133     /* Get the SPI IT index */
;;;1134     itpos = SPI_I2S_IT >> 4;
;;;1135
;;;1136     /* Set the IT mask */
;;;1137     itmask = (uint16_t)1 << (uint16_t)itpos;
000002  2301              MOVS     r3,#1
000004  408b              LSLS     r3,r3,r1
000006  b299              UXTH     r1,r3
;;;1138
;;;1139     if (NewState != DISABLE)
000008  2a00              CMP      r2,#0
00000a  d003              BEQ      |L17.20|
;;;1140     {
;;;1141       /* Enable the selected SPI interrupt */
;;;1142       SPIx->CR2 |= itmask;
00000c  8882              LDRH     r2,[r0,#4]
00000e  430a              ORRS     r2,r2,r1
000010  8082              STRH     r2,[r0,#4]
;;;1143     }
;;;1144     else
;;;1145     {
;;;1146       /* Disable the selected SPI interrupt */
;;;1147       SPIx->CR2 &= (uint16_t)~itmask;
;;;1148     }
;;;1149   }
000012  4770              BX       lr
                  |L17.20|
000014  8882              LDRH     r2,[r0,#4]            ;1147
000016  438a              BICS     r2,r2,r1              ;1147
000018  8082              STRH     r2,[r0,#4]            ;1147
00001a  4770              BX       lr
;;;1150
                          ENDP


                          AREA ||i.SPI_I2S_ReceiveData||, CODE, READONLY, ALIGN=1

                  SPI_I2S_ReceiveData PROC
;;;807      */
;;;808    uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
000000  8980              LDRH     r0,[r0,#0xc]
;;;809    {
;;;810      /* Check the parameters */
;;;811      assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
;;;812
;;;813      /* Return the data in the DR register */
;;;814      return SPIx->DR;
;;;815    }
000002  4770              BX       lr
;;;816
                          ENDP


                          AREA ||i.SPI_I2S_SendData||, CODE, READONLY, ALIGN=1

                  SPI_I2S_SendData PROC
;;;823      */
;;;824    void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
000000  8181              STRH     r1,[r0,#0xc]
;;;825    {
;;;826      /* Check the parameters */
;;;827      assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
;;;828
;;;829      /* Write in the DR register the data to be sent */
;;;830      SPIx->DR = Data;
;;;831    }
000002  4770              BX       lr
;;;832
                          ENDP


                          AREA ||i.SPI_Init||, CODE, READONLY, ALIGN=1

                  SPI_Init PROC
;;;283      */
;;;284    void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
000000  b530              PUSH     {r4,r5,lr}
;;;285    {
;;;286      uint16_t tmpreg = 0;
;;;287
;;;288      /* check the parameters */
;;;289      assert_param(IS_SPI_ALL_PERIPH(SPIx));
;;;290
;;;291      /* Check the SPI parameters */
;;;292      assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
;;;293      assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
;;;294      assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
;;;295      assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
;;;296      assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
;;;297      assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
;;;298      assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
;;;299      assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
;;;300      assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
;;;301
;;;302    /*---------------------------- SPIx CR1 Configuration ------------------------*/
;;;303      /* Get the SPIx CR1 value */
;;;304      tmpreg = SPIx->CR1;
000002  8802              LDRH     r2,[r0,#0]
;;;305      /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
;;;306      tmpreg &= CR1_CLEAR_MASK;
000004  f4025341          AND      r3,r2,#0x3040
;;;307      /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
;;;308         master/salve mode, CPOL and CPHA */
;;;309      /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
;;;310      /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
;;;311      /* Set LSBFirst bit according to SPI_FirstBit value */
;;;312      /* Set BR bits according to SPI_BaudRatePrescaler value */
;;;313      /* Set CPOL bit according to SPI_CPOL value */
;;;314      /* Set CPHA bit according to SPI_CPHA value */
;;;315      tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
000008  880a              LDRH     r2,[r1,#0]
00000a  884c              LDRH     r4,[r1,#2]
00000c  88cd              LDRH     r5,[r1,#6]
00000e  4322              ORRS     r2,r2,r4
000010  888c              LDRH     r4,[r1,#4]
000012  432c              ORRS     r4,r4,r5
000014  4322              ORRS     r2,r2,r4
000016  890c              LDRH     r4,[r1,#8]
000018  4322              ORRS     r2,r2,r4
00001a  894c              LDRH     r4,[r1,#0xa]
00001c  4322              ORRS     r2,r2,r4
00001e  898c              LDRH     r4,[r1,#0xc]
000020  4322              ORRS     r2,r2,r4
000022  89cc              LDRH     r4,[r1,#0xe]
000024  4322              ORRS     r2,r2,r4
000026  431a              ORRS     r2,r2,r3
;;;316                      SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
;;;317                      SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
;;;318                      SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
;;;319      /* Write to SPIx CR1 */
;;;320      SPIx->CR1 = tmpreg;
000028  8002              STRH     r2,[r0,#0]
;;;321
;;;322      /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
;;;323      SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
00002a  8b82              LDRH     r2,[r0,#0x1c]
00002c  f4226200          BIC      r2,r2,#0x800
000030  8382              STRH     r2,[r0,#0x1c]
;;;324    /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
;;;325      /* Write to SPIx CRCPOLY */
;;;326      SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
000032  8a09              LDRH     r1,[r1,#0x10]
000034  8201              STRH     r1,[r0,#0x10]
;;;327    }
000036  bd30              POP      {r4,r5,pc}
;;;328
                          ENDP


                          AREA ||i.SPI_NSSInternalSoftwareConfig||, CODE, READONLY, ALIGN=1

                  SPI_NSSInternalSoftwareConfig PROC
;;;641      */
;;;642    void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
000000  f5a1427e          SUB      r2,r1,#0xfe00
;;;643    {
;;;644      /* Check the parameters */
;;;645      assert_param(IS_SPI_ALL_PERIPH(SPIx));
;;;646      assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
;;;647      if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
000004  3aff              SUBS     r2,r2,#0xff
000006  d004              BEQ      |L21.18|
;;;648      {
;;;649        /* Set NSS pin internally by software */
;;;650        SPIx->CR1 |= SPI_NSSInternalSoft_Set;
000008  8801              LDRH     r1,[r0,#0]
00000a  f4417180          ORR      r1,r1,#0x100
00000e  8001              STRH     r1,[r0,#0]
;;;651      }
;;;652      else
;;;653      {
;;;654        /* Reset NSS pin internally by software */
;;;655        SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
;;;656      }
;;;657    }
000010  4770              BX       lr
                  |L21.18|
000012  8801              LDRH     r1,[r0,#0]            ;655
000014  f4217180          BIC      r1,r1,#0x100          ;655
000018  8001              STRH     r1,[r0,#0]            ;655
00001a  4770              BX       lr
;;;658
                          ENDP


                          AREA ||i.SPI_SSOutputCmd||, CODE, READONLY, ALIGN=1

                  SPI_SSOutputCmd PROC
;;;665      */
;;;666    void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;667    {
000002  d004              BEQ      |L22.14|
;;;668      /* Check the parameters */
;;;669      assert_param(IS_SPI_ALL_PERIPH(SPIx));
;;;670      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;671      if (NewState != DISABLE)
;;;672      {
;;;673        /* Enable the selected SPI SS output */
;;;674        SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
000004  8881              LDRH     r1,[r0,#4]
000006  f0410104          ORR      r1,r1,#4
00000a  8081              STRH     r1,[r0,#4]
;;;675      }
;;;676      else
;;;677      {
;;;678        /* Disable the selected SPI SS output */
;;;679        SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
;;;680      }
;;;681    }
00000c  4770              BX       lr
                  |L22.14|
00000e  8881              LDRH     r1,[r0,#4]            ;679
000010  f0210104          BIC      r1,r1,#4              ;679
000014  8081              STRH     r1,[r0,#4]            ;679
000016  4770              BX       lr
;;;682
                          ENDP


                          AREA ||i.SPI_StructInit||, CODE, READONLY, ALIGN=1

                  SPI_StructInit PROC
;;;486      */
;;;487    void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
000000  2100              MOVS     r1,#0
;;;488    {
;;;489    /*--------------- Reset SPI init structure parameters values -----------------*/
;;;490      /* Initialize the SPI_Direction member */
;;;491      SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
000002  8001              STRH     r1,[r0,#0]
;;;492      /* initialize the SPI_Mode member */
;;;493      SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
000004  8041              STRH     r1,[r0,#2]
;;;494      /* initialize the SPI_DataSize member */
;;;495      SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
000006  8081              STRH     r1,[r0,#4]
;;;496      /* Initialize the SPI_CPOL member */
;;;497      SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
000008  80c1              STRH     r1,[r0,#6]
;;;498      /* Initialize the SPI_CPHA member */
;;;499      SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
00000a  8101              STRH     r1,[r0,#8]
;;;500      /* Initialize the SPI_NSS member */
;;;501      SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
00000c  8141              STRH     r1,[r0,#0xa]
;;;502      /* Initialize the SPI_BaudRatePrescaler member */
;;;503      SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
00000e  8181              STRH     r1,[r0,#0xc]
;;;504      /* Initialize the SPI_FirstBit member */
;;;505      SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
000010  81c1              STRH     r1,[r0,#0xe]
;;;506      /* Initialize the SPI_CRCPolynomial member */
;;;507      SPI_InitStruct->SPI_CRCPolynomial = 7;
000012  2107              MOVS     r1,#7
000014  8201              STRH     r1,[r0,#0x10]
;;;508    }
000016  4770              BX       lr
;;;509
                          ENDP


                          AREA ||i.SPI_TIModeCmd||, CODE, READONLY, ALIGN=1

                  SPI_TIModeCmd PROC
;;;696      */
;;;697    void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;698    {
000002  d004              BEQ      |L24.14|
;;;699      /* Check the parameters */
;;;700      assert_param(IS_SPI_ALL_PERIPH(SPIx));
;;;701      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;702
;;;703      if (NewState != DISABLE)
;;;704      {
;;;705        /* Enable the TI mode for the selected SPI peripheral */
;;;706        SPIx->CR2 |= SPI_CR2_FRF;
000004  8881              LDRH     r1,[r0,#4]
000006  f0410110          ORR      r1,r1,#0x10
00000a  8081              STRH     r1,[r0,#4]
;;;707      }
;;;708      else
;;;709      {
;;;710        /* Disable the TI mode for the selected SPI peripheral */
;;;711        SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF;
;;;712      }
;;;713    }
00000c  4770              BX       lr
                  |L24.14|
00000e  8881              LDRH     r1,[r0,#4]            ;711
000010  f0210110          BIC      r1,r1,#0x10           ;711
000014  8081              STRH     r1,[r0,#4]            ;711
000016  4770              BX       lr
;;;714
                          ENDP


                          AREA ||i.SPI_TransmitCRC||, CODE, READONLY, ALIGN=1

                  SPI_TransmitCRC PROC
;;;935      */
;;;936    void SPI_TransmitCRC(SPI_TypeDef* SPIx)
000000  8801              LDRH     r1,[r0,#0]
;;;937    {
;;;938      /* Check the parameters */
;;;939      assert_param(IS_SPI_ALL_PERIPH(SPIx));
;;;940
;;;941      /* Enable the selected SPI CRC transmission */
;;;942      SPIx->CR1 |= SPI_CR1_CRCNEXT;
000002  f4415180          ORR      r1,r1,#0x1000
000006  8001              STRH     r1,[r0,#0]
;;;943    }
000008  4770              BX       lr
;;;944
                          ENDP


;*** Start embedded assembler ***

#line 1 "..\\..\\Libraries\\STM32F4xx_StdPeriph_Driver\\src\\stm32f4xx_spi.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f4xx_spi_c_2b928927____REV16|
#line 129 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h"
|__asm___15_stm32f4xx_spi_c_2b928927____REV16| PROC
#line 130

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f4xx_spi_c_2b928927____REVSH|
#line 144
|__asm___15_stm32f4xx_spi_c_2b928927____REVSH| PROC
#line 145

 revsh r0, r0
 bx lr
	ENDP
	AREA ||.rrx_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f4xx_spi_c_2b928927____RRX|
#line 300
|__asm___15_stm32f4xx_spi_c_2b928927____RRX| PROC
#line 301

 rrx r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***