AGV / agv_gelinmei · Files

; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\flash\obj\stm32f4xx_fsmc.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\stm32f4xx_fsmc.d --cpu=Cortex-M4.fp --apcs=interwork -O1 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Include -I..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\uCOS-III\uC-CPU -I..\..\uCOS-III\uC-LIB -I..\..\uCOS-III\uCOS-III\Ports -I..\..\uCOS-III\uCOS-III\Source -I..\..\uCOS-III\uC-CPU\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uC-LIB\Ports\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uCOS-III\Ports\ARM-Cortex-M4\Generic\RealView -I..\..\User -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\libapp -I..\..\RL-ARM\Config -I..\..\RL-ARM\Driver -I..\..\RL-ARM\RL-RTX\inc -I..\..\User\bsp\BSP -I..\..\RL-ARM\RL-CAN -I..\..\Libraries\DSP_LIB\Include -I..\..\MODBUS\modbus\rtu -I..\..\MODBUS\BARE\port -I..\..\MODBUS\modbus\include -I..\..\User\bsp\BSP -I..\..\PLC -I..\..\Avoid -I..\..\User\parameter -I..\..\User\LaserMotionCtr -I..\..\User\W5100S -I..\..\User\bsp -I..\..\User\CHASSIS -I..\..\User\CONTROLFUNCTION -I..\..\User\DATAUPDATE -I..\..\User\HARAWARE -I..\..\User\MOTORDRIVER -I..\..\User\NAVAGATION -I..\..\User\PLATFORM -I..\..\User\SENSOR -I.\RTE\_Flash -IC:\Users\YDJ\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include -IC:\Users\YDJ\AppData\Local\Arm\Packs\Keil\STM32F4xx_DFP\2.13.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include -D__UVISION_VERSION=527 -D_RTE_ -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -D__RTX -D__FPU_USED=1 --omf_browse=.\flash\obj\stm32f4xx_fsmc.crf ..\..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_fsmc.c]
                          THUMB

                          AREA ||i.FSMC_ClearFlag||, CODE, READONLY, ALIGN=1

                  FSMC_ClearFlag PROC
;;;979      */
;;;980    void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
000000  f04f4220          MOV      r2,#0xa0000000
;;;981    {
;;;982     /* Check the parameters */
;;;983      assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
;;;984      assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
;;;985        
;;;986      if(FSMC_Bank == FSMC_Bank2_NAND)
000004  2810              CMP      r0,#0x10
000006  d007              BEQ      |L1.24|
;;;987      {
;;;988        FSMC_Bank2->SR2 &= ~FSMC_FLAG; 
;;;989      }  
;;;990      else if(FSMC_Bank == FSMC_Bank3_NAND)
000008  f5b07f80          CMP      r0,#0x100
00000c  d008              BEQ      |L1.32|
;;;991      {
;;;992        FSMC_Bank3->SR3 &= ~FSMC_FLAG;
;;;993      }
;;;994      /* FSMC_Bank4_PCCARD*/
;;;995      else
;;;996      {
;;;997        FSMC_Bank4->SR4 &= ~FSMC_FLAG;
00000e  f8520fa4          LDR      r0,[r2,#0xa4]!
000012  4388              BICS     r0,r0,r1
000014  6010              STR      r0,[r2,#0]
;;;998      }
;;;999    }
000016  4770              BX       lr
                  |L1.24|
000018  6e50              LDR      r0,[r2,#0x64]         ;988
00001a  4388              BICS     r0,r0,r1              ;988
00001c  6650              STR      r0,[r2,#0x64]         ;988
00001e  4770              BX       lr
                  |L1.32|
000020  f8520f84          LDR      r0,[r2,#0x84]!        ;992
000024  4388              BICS     r0,r0,r1              ;992
000026  6010              STR      r0,[r2,#0]            ;992
000028  4770              BX       lr
;;;1000   
                          ENDP


                          AREA ||i.FSMC_ClearITPendingBit||, CODE, READONLY, ALIGN=1

                  FSMC_ClearITPendingBit PROC
;;;1065     */
;;;1066   void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
000000  f04f4220          MOV      r2,#0xa0000000
;;;1067   {
;;;1068     /* Check the parameters */
;;;1069     assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
;;;1070     assert_param(IS_FSMC_IT(FSMC_IT));
;;;1071       
;;;1072     if(FSMC_Bank == FSMC_Bank2_NAND)
000004  2810              CMP      r0,#0x10
000006  d008              BEQ      |L2.26|
;;;1073     {
;;;1074       FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); 
;;;1075     }  
;;;1076     else if(FSMC_Bank == FSMC_Bank3_NAND)
000008  f5b07f80          CMP      r0,#0x100
00000c  d00a              BEQ      |L2.36|
;;;1077     {
;;;1078       FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
;;;1079     }
;;;1080     /* FSMC_Bank4_PCCARD*/
;;;1081     else
;;;1082     {
;;;1083       FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
00000e  f8520fa4          LDR      r0,[r2,#0xa4]!
000012  ea2000d1          BIC      r0,r0,r1,LSR #3
000016  6010              STR      r0,[r2,#0]
;;;1084     }
;;;1085   }
000018  4770              BX       lr
                  |L2.26|
00001a  6e50              LDR      r0,[r2,#0x64]         ;1074
00001c  ea2000d1          BIC      r0,r0,r1,LSR #3       ;1074
000020  6650              STR      r0,[r2,#0x64]         ;1074
000022  4770              BX       lr
                  |L2.36|
000024  f8520f84          LDR      r0,[r2,#0x84]!        ;1078
000028  ea2000d1          BIC      r0,r0,r1,LSR #3       ;1078
00002c  6010              STR      r0,[r2,#0]            ;1078
00002e  4770              BX       lr
;;;1086   
                          ENDP


                          AREA ||i.FSMC_GetECC||, CODE, READONLY, ALIGN=1

                  FSMC_GetECC PROC
;;;625      */
;;;626    uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
000000  f04f4120          MOV      r1,#0xa0000000
;;;627    {
;;;628      uint32_t eccval = 0x00000000;
;;;629      
;;;630      if(FSMC_Bank == FSMC_Bank2_NAND)
000004  2810              CMP      r0,#0x10
000006  d002              BEQ      |L3.14|
;;;631      {
;;;632        /* Get the ECCR2 register value */
;;;633        eccval = FSMC_Bank2->ECCR2;
;;;634      }
;;;635      else
;;;636      {
;;;637        /* Get the ECCR3 register value */
;;;638        eccval = FSMC_Bank3->ECCR3;
000008  f8d10094          LDR      r0,[r1,#0x94]
;;;639      }
;;;640      /* Return the error correction code value */
;;;641      return(eccval);
;;;642    }
00000c  4770              BX       lr
                  |L3.14|
00000e  6f48              LDR      r0,[r1,#0x74]         ;633
000010  4770              BX       lr
;;;643    /**
                          ENDP


                          AREA ||i.FSMC_GetFlagStatus||, CODE, READONLY, ALIGN=1

                  FSMC_GetFlagStatus PROC
;;;929      */
;;;930    FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
000000  4603              MOV      r3,r0
;;;931    {
;;;932      FlagStatus bitstatus = RESET;
000002  2000              MOVS     r0,#0
;;;933      uint32_t tmpsr = 0x00000000;
;;;934      
;;;935      /* Check the parameters */
;;;936      assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
;;;937      assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
;;;938      
;;;939      if(FSMC_Bank == FSMC_Bank2_NAND)
;;;940      {
;;;941        tmpsr = FSMC_Bank2->SR2;
000004  f04f4220          MOV      r2,#0xa0000000
000008  2b10              CMP      r3,#0x10              ;939
00000a  d008              BEQ      |L4.30|
;;;942      }  
;;;943      else if(FSMC_Bank == FSMC_Bank3_NAND)
00000c  f5b37f80          CMP      r3,#0x100
000010  d007              BEQ      |L4.34|
;;;944      {
;;;945        tmpsr = FSMC_Bank3->SR3;
;;;946      }
;;;947      /* FSMC_Bank4_PCCARD*/
;;;948      else
;;;949      {
;;;950        tmpsr = FSMC_Bank4->SR4;
000012  f8d220a4          LDR      r2,[r2,#0xa4]
                  |L4.22|
;;;951      } 
;;;952      
;;;953      /* Get the flag status */
;;;954      if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
000016  420a              TST      r2,r1
000018  d000              BEQ      |L4.28|
;;;955      {
;;;956        bitstatus = SET;
00001a  2001              MOVS     r0,#1
                  |L4.28|
;;;957      }
;;;958      else
;;;959      {
;;;960        bitstatus = RESET;
;;;961      }
;;;962      /* Return the flag status */
;;;963      return bitstatus;
;;;964    }
00001c  4770              BX       lr
                  |L4.30|
00001e  6e52              LDR      r2,[r2,#0x64]         ;941
000020  e7f9              B        |L4.22|
                  |L4.34|
000022  f8d22084          LDR      r2,[r2,#0x84]         ;945
000026  e7f6              B        |L4.22|
;;;965    
                          ENDP


                          AREA ||i.FSMC_GetITStatus||, CODE, READONLY, ALIGN=1

                  FSMC_GetITStatus PROC
;;;1014     */
;;;1015   ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
000000  4603              MOV      r3,r0
;;;1016   {
;;;1017     ITStatus bitstatus = RESET;
000002  2000              MOVS     r0,#0
;;;1018     uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; 
;;;1019     
;;;1020     /* Check the parameters */
;;;1021     assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
;;;1022     assert_param(IS_FSMC_GET_IT(FSMC_IT));
;;;1023     
;;;1024     if(FSMC_Bank == FSMC_Bank2_NAND)
;;;1025     {
;;;1026       tmpsr = FSMC_Bank2->SR2;
000004  f04f4220          MOV      r2,#0xa0000000
000008  2b10              CMP      r3,#0x10              ;1024
00000a  d00e              BEQ      |L5.42|
;;;1027     }  
;;;1028     else if(FSMC_Bank == FSMC_Bank3_NAND)
00000c  f5b37f80          CMP      r3,#0x100
000010  d00d              BEQ      |L5.46|
;;;1029     {
;;;1030       tmpsr = FSMC_Bank3->SR3;
;;;1031     }
;;;1032     /* FSMC_Bank4_PCCARD*/
;;;1033     else
;;;1034     {
;;;1035       tmpsr = FSMC_Bank4->SR4;
000012  f8d220a4          LDR      r2,[r2,#0xa4]
                  |L5.22|
;;;1036     } 
;;;1037     
;;;1038     itstatus = tmpsr & FSMC_IT;
000016  ea020301          AND      r3,r2,r1
;;;1039     
;;;1040     itenable = tmpsr & (FSMC_IT >> 3);
00001a  ea0201d1          AND      r1,r2,r1,LSR #3
;;;1041     if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))
00001e  2b00              CMP      r3,#0
000020  d002              BEQ      |L5.40|
000022  2900              CMP      r1,#0
000024  d000              BEQ      |L5.40|
;;;1042     {
;;;1043       bitstatus = SET;
000026  2001              MOVS     r0,#1
                  |L5.40|
;;;1044     }
;;;1045     else
;;;1046     {
;;;1047       bitstatus = RESET;
;;;1048     }
;;;1049     return bitstatus; 
;;;1050   }
000028  4770              BX       lr
                  |L5.42|
00002a  6e52              LDR      r2,[r2,#0x64]         ;1026
00002c  e7f3              B        |L5.22|
                  |L5.46|
00002e  f8d22084          LDR      r2,[r2,#0x84]         ;1030
000032  e7f0              B        |L5.22|
;;;1051   
                          ENDP


                          AREA ||i.FSMC_ITConfig||, CODE, READONLY, ALIGN=1

                  FSMC_ITConfig PROC
;;;869      */
;;;870    void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
000000  b510              PUSH     {r4,lr}
;;;871    {
;;;872      assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
;;;873      assert_param(IS_FSMC_IT(FSMC_IT));	
;;;874      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;875      
;;;876      if (NewState != DISABLE)
;;;877      {
;;;878        /* Enable the selected FSMC_Bank2 interrupts */
;;;879        if(FSMC_Bank == FSMC_Bank2_NAND)
;;;880        {
;;;881          FSMC_Bank2->SR2 |= FSMC_IT;
;;;882        }
;;;883        /* Enable the selected FSMC_Bank3 interrupts */
;;;884        else if (FSMC_Bank == FSMC_Bank3_NAND)
000002  f44f7480          MOV      r4,#0x100
000006  f04f4320          MOV      r3,#0xa0000000        ;881
00000a  2a00              CMP      r2,#0                 ;876
00000c  d011              BEQ      |L6.50|
00000e  2810              CMP      r0,#0x10              ;879
000010  d006              BEQ      |L6.32|
000012  42a0              CMP      r0,r4
000014  d108              BNE      |L6.40|
;;;885        {
;;;886          FSMC_Bank3->SR3 |= FSMC_IT;
000016  f8530f84          LDR      r0,[r3,#0x84]!
00001a  4308              ORRS     r0,r0,r1
00001c  6018              STR      r0,[r3,#0]
;;;887        }
;;;888        /* Enable the selected FSMC_Bank4 interrupts */
;;;889        else
;;;890        {
;;;891          FSMC_Bank4->SR4 |= FSMC_IT;    
;;;892        }
;;;893      }
;;;894      else
;;;895      {
;;;896        /* Disable the selected FSMC_Bank2 interrupts */
;;;897        if(FSMC_Bank == FSMC_Bank2_NAND)
;;;898        {
;;;899          
;;;900          FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
;;;901        }
;;;902        /* Disable the selected FSMC_Bank3 interrupts */
;;;903        else if (FSMC_Bank == FSMC_Bank3_NAND)
;;;904        {
;;;905          FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
;;;906        }
;;;907        /* Disable the selected FSMC_Bank4 interrupts */
;;;908        else
;;;909        {
;;;910          FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;    
;;;911        }
;;;912      }
;;;913    }
00001e  bd10              POP      {r4,pc}
                  |L6.32|
000020  6e58              LDR      r0,[r3,#0x64]         ;881
000022  4308              ORRS     r0,r0,r1              ;881
000024  6658              STR      r0,[r3,#0x64]         ;881
000026  bd10              POP      {r4,pc}
                  |L6.40|
000028  f8530fa4          LDR      r0,[r3,#0xa4]!        ;891
00002c  4308              ORRS     r0,r0,r1              ;891
00002e  6018              STR      r0,[r3,#0]            ;891
000030  bd10              POP      {r4,pc}
                  |L6.50|
000032  2810              CMP      r0,#0x10              ;897
000034  d006              BEQ      |L6.68|
000036  42a0              CMP      r0,r4                 ;903
000038  d108              BNE      |L6.76|
00003a  f8530f84          LDR      r0,[r3,#0x84]!        ;905
00003e  4388              BICS     r0,r0,r1              ;905
000040  6018              STR      r0,[r3,#0]            ;905
000042  bd10              POP      {r4,pc}
                  |L6.68|
000044  6e58              LDR      r0,[r3,#0x64]         ;900
000046  4388              BICS     r0,r0,r1              ;900
000048  6658              STR      r0,[r3,#0x64]         ;900
00004a  bd10              POP      {r4,pc}
                  |L6.76|
00004c  f8530fa4          LDR      r0,[r3,#0xa4]!        ;910
000050  4388              BICS     r0,r0,r1              ;910
000052  6018              STR      r0,[r3,#0]            ;910
000054  bd10              POP      {r4,pc}
;;;914    
                          ENDP


                          AREA ||i.FSMC_NANDCmd||, CODE, READONLY, ALIGN=2

                  FSMC_NANDCmd PROC
;;;546      */
;;;547    void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
000000  f04f4220          MOV      r2,#0xa0000000
;;;548    {
;;;549      assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
;;;550      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;551      
;;;552      if (NewState != DISABLE)
000004  2900              CMP      r1,#0
000006  d00c              BEQ      |L7.34|
;;;553      {
;;;554        /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
;;;555        if(FSMC_Bank == FSMC_Bank2_NAND)
000008  2810              CMP      r0,#0x10
00000a  d005              BEQ      |L7.24|
;;;556        {
;;;557          FSMC_Bank2->PCR2 |= PCR_PBKEN_SET;
;;;558        }
;;;559        else
;;;560        {
;;;561          FSMC_Bank3->PCR3 |= PCR_PBKEN_SET;
00000c  f8520f80          LDR      r0,[r2,#0x80]!
000010  f0400004          ORR      r0,r0,#4
000014  6010              STR      r0,[r2,#0]
;;;562        }
;;;563      }
;;;564      else
;;;565      {
;;;566        /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
;;;567        if(FSMC_Bank == FSMC_Bank2_NAND)
;;;568        {
;;;569          FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET;
;;;570        }
;;;571        else
;;;572        {
;;;573          FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET;
;;;574        }
;;;575      }
;;;576    }
000016  4770              BX       lr
                  |L7.24|
000018  6e10              LDR      r0,[r2,#0x60]         ;557
00001a  f0400004          ORR      r0,r0,#4              ;557
00001e  6610              STR      r0,[r2,#0x60]         ;557
000020  4770              BX       lr
                  |L7.34|
000022  4906              LDR      r1,|L7.60|
000024  2810              CMP      r0,#0x10              ;567
000026  d004              BEQ      |L7.50|
000028  f8520f80          LDR      r0,[r2,#0x80]!        ;573
00002c  4008              ANDS     r0,r0,r1              ;573
00002e  6010              STR      r0,[r2,#0]            ;573
000030  4770              BX       lr
                  |L7.50|
000032  6e10              LDR      r0,[r2,#0x60]         ;569
000034  4008              ANDS     r0,r0,r1              ;569
000036  6610              STR      r0,[r2,#0x60]         ;569
000038  4770              BX       lr
;;;577    /**
                          ENDP

00003a  0000              DCW      0x0000
                  |L7.60|
                          DCD      0x000ffffb

                          AREA ||i.FSMC_NANDDeInit||, CODE, READONLY, ALIGN=1

                  FSMC_NANDDeInit PROC
;;;375      */
;;;376    void FSMC_NANDDeInit(uint32_t FSMC_Bank)
000000  b510              PUSH     {r4,lr}
;;;377    {
;;;378      /* Check the parameter */
;;;379      assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
;;;380      
;;;381      if(FSMC_Bank == FSMC_Bank2_NAND)
;;;382      {
;;;383        /* Set the FSMC_Bank2 registers to their reset values */
;;;384        FSMC_Bank2->PCR2 = 0x00000018;
000002  2418              MOVS     r4,#0x18
;;;385        FSMC_Bank2->SR2 = 0x00000040;
000004  2340              MOVS     r3,#0x40
000006  f04f4120          MOV      r1,#0xa0000000        ;384
;;;386        FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
00000a  f04f32fc          MOV      r2,#0xfcfcfcfc
00000e  2810              CMP      r0,#0x10              ;381
000010  d005              BEQ      |L8.30|
;;;387        FSMC_Bank2->PATT2 = 0xFCFCFCFC;  
;;;388      }
;;;389      /* FSMC_Bank3_NAND */  
;;;390      else
;;;391      {
;;;392        /* Set the FSMC_Bank3 registers to their reset values */
;;;393        FSMC_Bank3->PCR3 = 0x00000018;
000012  f8414f80          STR      r4,[r1,#0x80]!
;;;394        FSMC_Bank3->SR3 = 0x00000040;
000016  604b              STR      r3,[r1,#4]
;;;395        FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
000018  608a              STR      r2,[r1,#8]
;;;396        FSMC_Bank3->PATT3 = 0xFCFCFCFC; 
00001a  60ca              STR      r2,[r1,#0xc]
;;;397      }  
;;;398    }
00001c  bd10              POP      {r4,pc}
                  |L8.30|
00001e  660c              STR      r4,[r1,#0x60]         ;384
000020  664b              STR      r3,[r1,#0x64]         ;385
000022  668a              STR      r2,[r1,#0x68]         ;386
000024  66ca              STR      r2,[r1,#0x6c]         ;387
000026  bd10              POP      {r4,pc}
;;;399    
                          ENDP


                          AREA ||i.FSMC_NANDECCCmd||, CODE, READONLY, ALIGN=2

                  FSMC_NANDECCCmd PROC
;;;586      */
;;;587    void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
000000  f04f4220          MOV      r2,#0xa0000000
;;;588    {
;;;589      assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
;;;590      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;591      
;;;592      if (NewState != DISABLE)
000004  2900              CMP      r1,#0
000006  d00c              BEQ      |L9.34|
;;;593      {
;;;594        /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
;;;595        if(FSMC_Bank == FSMC_Bank2_NAND)
000008  2810              CMP      r0,#0x10
00000a  d005              BEQ      |L9.24|
;;;596        {
;;;597          FSMC_Bank2->PCR2 |= PCR_ECCEN_SET;
;;;598        }
;;;599        else
;;;600        {
;;;601          FSMC_Bank3->PCR3 |= PCR_ECCEN_SET;
00000c  f8520f80          LDR      r0,[r2,#0x80]!
000010  f0400040          ORR      r0,r0,#0x40
000014  6010              STR      r0,[r2,#0]
;;;602        }
;;;603      }
;;;604      else
;;;605      {
;;;606        /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
;;;607        if(FSMC_Bank == FSMC_Bank2_NAND)
;;;608        {
;;;609          FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET;
;;;610        }
;;;611        else
;;;612        {
;;;613          FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET;
;;;614        }
;;;615      }
;;;616    }
000016  4770              BX       lr
                  |L9.24|
000018  6e10              LDR      r0,[r2,#0x60]         ;597
00001a  f0400040          ORR      r0,r0,#0x40           ;597
00001e  6610              STR      r0,[r2,#0x60]         ;597
000020  4770              BX       lr
                  |L9.34|
000022  4906              LDR      r1,|L9.60|
000024  2810              CMP      r0,#0x10              ;607
000026  d004              BEQ      |L9.50|
000028  f8520f80          LDR      r0,[r2,#0x80]!        ;613
00002c  4008              ANDS     r0,r0,r1              ;613
00002e  6010              STR      r0,[r2,#0]            ;613
000030  4770              BX       lr
                  |L9.50|
000032  6e10              LDR      r0,[r2,#0x60]         ;609
000034  4008              ANDS     r0,r0,r1              ;609
000036  6610              STR      r0,[r2,#0x60]         ;609
000038  4770              BX       lr
;;;617    
                          ENDP

00003a  0000              DCW      0x0000
                  |L9.60|
                          DCD      0x000fffbf

                          AREA ||i.FSMC_NANDInit||, CODE, READONLY, ALIGN=2

                  FSMC_NANDInit PROC
;;;406      */
;;;407    void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
000000  b530              PUSH     {r4,r5,lr}
;;;408    {
;;;409      uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; 
;;;410        
;;;411      /* Check the parameters */
;;;412      assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
;;;413      assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
;;;414      assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
;;;415      assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
;;;416      assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
;;;417      assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
;;;418      assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
;;;419      assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
;;;420      assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
;;;421      assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
;;;422      assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
;;;423      assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
;;;424      assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
;;;425      assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
;;;426      assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
;;;427      
;;;428      if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
000002  6802              LDR      r2,[r0,#0]
;;;429      {
;;;430      /* Get the NAND bank 2 register value */
;;;431        tmppcr = FSMC_Bank2->PCR2;
000004  f04f4120          MOV      r1,#0xa0000000
000008  2a10              CMP      r2,#0x10              ;428
00000a  d01b              BEQ      |L10.68|
;;;432      }
;;;433      else
;;;434      {
;;;435      /* Get the NAND bank 3 register value */
;;;436        tmppcr = FSMC_Bank3->PCR3;
00000c  f8d12080          LDR      r2,[r1,#0x80]
                  |L10.16|
;;;437      }
;;;438    
;;;439      /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
;;;440      tmppcr &= ((uint32_t)~(FSMC_PCR2_PWAITEN  | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \
000010  4b22              LDR      r3,|L10.156|
000012  ea020203          AND      r2,r2,r3
;;;441                             FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
;;;442                             FSMC_PCR2_TAR | FSMC_PCR2_ECCPS));  
;;;443    					   
;;;444      /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
;;;445      tmppcr |= (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
000016  e9d03401          LDRD     r3,r4,[r0,#4]
00001a  ea430304          ORR      r3,r3,r4
00001e  e9d04503          LDRD     r4,r5,[r0,#0xc]
000022  ea440405          ORR      r4,r4,r5
000026  ea430304          ORR      r3,r3,r4
00002a  6944              LDR      r4,[r0,#0x14]
00002c  ea432344          ORR      r3,r3,r4,LSL #9
000030  6984              LDR      r4,[r0,#0x18]
000032  ea433344          ORR      r3,r3,r4,LSL #13
000036  ea430302          ORR      r3,r3,r2
00003a  f0430408          ORR      r4,r3,#8
;;;446                          PCR_MEMORYTYPE_NAND |
;;;447                          FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
;;;448                          FSMC_NANDInitStruct->FSMC_ECC |
;;;449                          FSMC_NANDInitStruct->FSMC_ECCPageSize |
;;;450                          (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
;;;451                          (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
;;;452        
;;;453      if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
00003e  d103              BNE      |L10.72|
;;;454      {
;;;455        /* Get the NAND bank 2 register value */
;;;456        tmppmem = FSMC_Bank2->PMEM2;
000040  6e8a              LDR      r2,[r1,#0x68]
000042  e003              B        |L10.76|
                  |L10.68|
000044  6e0a              LDR      r2,[r1,#0x60]         ;431
000046  e7e3              B        |L10.16|
                  |L10.72|
;;;457      }
;;;458      else
;;;459      {
;;;460        /* Get the NAND bank 3 register value */
;;;461        tmppmem = FSMC_Bank3->PMEM3;
000048  f8d12088          LDR      r2,[r1,#0x88]
                  |L10.76|
;;;462      } 
;;;463      
;;;464      /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
;;;465      tmppmem &= ((uint32_t)~(FSMC_PMEM2_MEMSET2  | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
;;;466                              FSMC_PMEM2_MEMHIZ2));
;;;467    					   
;;;468      /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
;;;469      tmppmem |= (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
00004c  69c2              LDR      r2,[r0,#0x1c]
00004e  e9d23500          LDRD     r3,r5,[r2,#0]
000052  ea432305          ORR      r3,r3,r5,LSL #8
000056  8915              LDRH     r5,[r2,#8]
000058  7b12              LDRB     r2,[r2,#0xc]
00005a  ea4f4505          LSL      r5,r5,#16
00005e  ea456202          ORR      r2,r5,r2,LSL #24
000062  ea430302          ORR      r3,r3,r2
;;;470                           (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;471                           (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;472                           (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
;;;473    
;;;474      if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
000066  d101              BNE      |L10.108|
;;;475      {
;;;476        /* Get the NAND bank 2 register value */
;;;477        tmppatt = FSMC_Bank2->PATT2;
000068  6eca              LDR      r2,[r1,#0x6c]
00006a  e000              B        |L10.110|
                  |L10.108|
;;;478      }
;;;479      else
;;;480      {
;;;481        /* Get the NAND bank 3 register value */
;;;482        tmppatt = FSMC_Bank2->PATT2;
00006c  6eca              LDR      r2,[r1,#0x6c]
                  |L10.110|
;;;483      } 
;;;484      
;;;485      /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
;;;486      tmppatt &= ((uint32_t)~(FSMC_PATT2_ATTSET2  | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
;;;487                              FSMC_PATT2_ATTHIZ2));
;;;488      
;;;489      /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
;;;490      tmppatt |= (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
00006e  6a00              LDR      r0,[r0,#0x20]
000070  e9d02500          LDRD     r2,r5,[r0,#0]
000074  ea422205          ORR      r2,r2,r5,LSL #8
000078  8905              LDRH     r5,[r0,#8]
00007a  7b00              LDRB     r0,[r0,#0xc]
00007c  ea4f4505          LSL      r5,r5,#16
000080  ea456000          ORR      r0,r5,r0,LSL #24
000084  ea420200          ORR      r2,r2,r0
;;;491                           (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;492                           (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;493                           (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
;;;494      
;;;495      if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
000088  d103              BNE      |L10.146|
;;;496      {
;;;497        /* FSMC_Bank2_NAND registers configuration */
;;;498        FSMC_Bank2->PCR2 = tmppcr;
00008a  660c              STR      r4,[r1,#0x60]
;;;499        FSMC_Bank2->PMEM2 = tmppmem;
00008c  668b              STR      r3,[r1,#0x68]
;;;500        FSMC_Bank2->PATT2 = tmppatt;
00008e  66ca              STR      r2,[r1,#0x6c]
;;;501      }
;;;502      else
;;;503      {
;;;504        /* FSMC_Bank3_NAND registers configuration */
;;;505        FSMC_Bank3->PCR3 = tmppcr;
;;;506        FSMC_Bank3->PMEM3 = tmppmem;
;;;507        FSMC_Bank3->PATT3 = tmppatt;
;;;508      }
;;;509    }
000090  bd30              POP      {r4,r5,pc}
                  |L10.146|
000092  f8414f80          STR      r4,[r1,#0x80]!        ;505
000096  608b              STR      r3,[r1,#8]            ;506
000098  60ca              STR      r2,[r1,#0xc]          ;507
00009a  bd30              POP      {r4,r5,pc}
;;;510    
                          ENDP

                  |L10.156|
                          DCD      0xfff00181

                          AREA ||i.FSMC_NANDStructInit||, CODE, READONLY, ALIGN=1

                  FSMC_NANDStructInit PROC
;;;517      */
;;;518    void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
000000  2110              MOVS     r1,#0x10
;;;519    { 
;;;520      /* Reset NAND Init structure parameters values */
;;;521      FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
000002  6001              STR      r1,[r0,#0]
;;;522      FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
000004  2100              MOVS     r1,#0
000006  6041              STR      r1,[r0,#4]
;;;523      FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
000008  6081              STR      r1,[r0,#8]
;;;524      FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
00000a  60c1              STR      r1,[r0,#0xc]
;;;525      FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
00000c  6101              STR      r1,[r0,#0x10]
;;;526      FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
00000e  6141              STR      r1,[r0,#0x14]
;;;527      FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
000010  6181              STR      r1,[r0,#0x18]
;;;528      FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
000012  69c2              LDR      r2,[r0,#0x1c]
000014  21fc              MOVS     r1,#0xfc
000016  6011              STR      r1,[r2,#0]
;;;529      FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
000018  69c2              LDR      r2,[r0,#0x1c]
00001a  6051              STR      r1,[r2,#4]
;;;530      FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00001c  69c2              LDR      r2,[r0,#0x1c]
00001e  6091              STR      r1,[r2,#8]
;;;531      FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000020  69c2              LDR      r2,[r0,#0x1c]
000022  60d1              STR      r1,[r2,#0xc]
;;;532      FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
000024  6a02              LDR      r2,[r0,#0x20]
000026  6011              STR      r1,[r2,#0]
;;;533      FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
000028  6a02              LDR      r2,[r0,#0x20]
00002a  6051              STR      r1,[r2,#4]
;;;534      FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00002c  6a02              LDR      r2,[r0,#0x20]
00002e  6091              STR      r1,[r2,#8]
;;;535      FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;	  
000030  6a00              LDR      r0,[r0,#0x20]
000032  60c1              STR      r1,[r0,#0xc]
;;;536    }
000034  4770              BX       lr
;;;537    
                          ENDP


                          AREA ||i.FSMC_NORSRAMCmd||, CODE, READONLY, ALIGN=2

                  FSMC_NORSRAMCmd PROC
;;;302      */
;;;303    void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
000000  0080              LSLS     r0,r0,#2
;;;304    {
;;;305      assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
;;;306      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;307      
;;;308      if (NewState != DISABLE)
;;;309      {
;;;310        /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
;;;311        FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET;
000002  f1a040c0          SUB      r0,r0,#0x60000000
000006  2900              CMP      r1,#0                 ;308
000008  d004              BEQ      |L12.20|
00000a  6801              LDR      r1,[r0,#0]
00000c  f0410101          ORR      r1,r1,#1
000010  6001              STR      r1,[r0,#0]
;;;312      }
;;;313      else
;;;314      {
;;;315        /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
;;;316        FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET;
;;;317      }
;;;318    }
000012  4770              BX       lr
                  |L12.20|
000014  6801              LDR      r1,[r0,#0]            ;316
000016  4a02              LDR      r2,|L12.32|
000018  4011              ANDS     r1,r1,r2              ;316
00001a  6001              STR      r1,[r0,#0]            ;316
00001c  4770              BX       lr
;;;319    /**
                          ENDP

00001e  0000              DCW      0x0000
                  |L12.32|
                          DCD      0x000ffffe

                          AREA ||i.FSMC_NORSRAMDeInit||, CODE, READONLY, ALIGN=1

                  FSMC_NORSRAMDeInit PROC
;;;128      */
;;;129    void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
000000  0081              LSLS     r1,r0,#2
;;;130    {
;;;131      /* Check the parameter */
;;;132      assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
;;;133      
;;;134      /* FSMC_Bank1_NORSRAM1 */
;;;135      if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
;;;136      {
;;;137        FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;    
;;;138      }
;;;139      /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
;;;140      else
;;;141      {   
;;;142        FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; 
000002  f1a141c0          SUB      r1,r1,#0x60000000
000006  2800              CMP      r0,#0                 ;135
000008  d00c              BEQ      |L13.36|
00000a  f24302d2          MOV      r2,#0x30d2
00000e  600a              STR      r2,[r1,#0]
                  |L13.16|
;;;143      }
;;;144      FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
000010  1c40              ADDS     r0,r0,#1
000012  0080              LSLS     r0,r0,#2
000014  f1a040c0          SUB      r0,r0,#0x60000000
000018  f06f4270          MVN      r2,#0xf0000000
00001c  6002              STR      r2,[r0,#0]
;;;145      FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;  
00001e  f8c12104          STR      r2,[r1,#0x104]
;;;146    }
000022  4770              BX       lr
                  |L13.36|
000024  f04f4320          MOV      r3,#0xa0000000        ;137
000028  f24302db          MOV      r2,#0x30db            ;137
00002c  601a              STR      r2,[r3,#0]            ;137
00002e  e7ef              B        |L13.16|
;;;147    
                          ENDP


                          AREA ||i.FSMC_NORSRAMInit||, CODE, READONLY, ALIGN=2

                  FSMC_NORSRAMInit PROC
;;;155      */
;;;156    void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
000000  b570              PUSH     {r4-r6,lr}
;;;157    { 
;;;158      uint32_t tmpbcr = 0, tmpbtr = 0, tmpbwr = 0;
;;;159    
;;;160      /* Check the parameters */
;;;161      assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
;;;162      assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
;;;163      assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
;;;164      assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
;;;165      assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
;;;166      assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
;;;167      assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
;;;168      assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
;;;169      assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
;;;170      assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
;;;171      assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
;;;172      assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
;;;173      assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));  
;;;174      assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
;;;175      assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
;;;176      assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
;;;177      assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
;;;178      assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
;;;179      assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
;;;180      assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); 
;;;181    
;;;182      /* Get the BTCR register value */
;;;183      tmpbcr = FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank];
000002  6801              LDR      r1,[r0,#0]
000004  0089              LSLS     r1,r1,#2
000006  f1a141c0          SUB      r1,r1,#0x60000000
00000a  680b              LDR      r3,[r1,#0]
;;;184    
;;;185      /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
;;;186               WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
;;;187      tmpbcr &= ((uint32_t)~(FSMC_BCR1_MBKEN    | FSMC_BCR1_MUXEN    | FSMC_BCR1_MTYP     | \
00000c  4a35              LDR      r2,|L14.228|
00000e  4013              ANDS     r3,r3,r2
;;;188                             FSMC_BCR1_MWID      | FSMC_BCR1_FACCEN   | FSMC_BCR1_BURSTEN  | \
;;;189                             FSMC_BCR1_WAITPOL   | FSMC_BCR1_WRAPMOD  | FSMC_BCR1_WAITCFG  | \
;;;190                             FSMC_BCR1_WREN      | FSMC_BCR1_WAITEN   | FSMC_BCR1_EXTMOD   | \
;;;191                             FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CBURSTRW));
;;;192    
;;;193      /* Bank1 NOR/SRAM control register configuration */ 
;;;194      tmpbcr |= (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
000010  e9d02401          LDRD     r2,r4,[r0,#4]
000014  4322              ORRS     r2,r2,r4
000016  e9d04503          LDRD     r4,r5,[r0,#0xc]
00001a  432c              ORRS     r4,r4,r5
00001c  4322              ORRS     r2,r2,r4
00001e  6944              LDR      r4,[r0,#0x14]
000020  4322              ORRS     r2,r2,r4
000022  6984              LDR      r4,[r0,#0x18]
000024  4322              ORRS     r2,r2,r4
000026  69c4              LDR      r4,[r0,#0x1c]
000028  4322              ORRS     r2,r2,r4
00002a  6a04              LDR      r4,[r0,#0x20]
00002c  4322              ORRS     r2,r2,r4
00002e  6a44              LDR      r4,[r0,#0x24]
000030  4322              ORRS     r2,r2,r4
000032  6a84              LDR      r4,[r0,#0x28]
000034  4322              ORRS     r2,r2,r4
000036  6ac4              LDR      r4,[r0,#0x2c]
000038  4322              ORRS     r2,r2,r4
00003a  6b04              LDR      r4,[r0,#0x30]
00003c  4322              ORRS     r2,r2,r4
00003e  431a              ORRS     r2,r2,r3
;;;195                FSMC_NORSRAMInitStruct->FSMC_MemoryType |
;;;196                FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
;;;197                FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
;;;198                FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
;;;199                FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
;;;200                FSMC_NORSRAMInitStruct->FSMC_WrapMode |
;;;201                FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
;;;202                FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
;;;203                FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
;;;204                FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
;;;205                FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
;;;206    			
;;;207      FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = tmpbcr;
000040  600a              STR      r2,[r1,#0]
;;;208      
;;;209      if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
000042  6881              LDR      r1,[r0,#8]
000044  2908              CMP      r1,#8
000046  d107              BNE      |L14.88|
;;;210      {
;;;211        FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
000048  6801              LDR      r1,[r0,#0]
00004a  0089              LSLS     r1,r1,#2
00004c  f1a141c0          SUB      r1,r1,#0x60000000
000050  680a              LDR      r2,[r1,#0]
000052  f0420240          ORR      r2,r2,#0x40
000056  600a              STR      r2,[r1,#0]
                  |L14.88|
;;;212      }
;;;213      
;;;214      /* Get the BTCR register value */
;;;215      tmpbtr = FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1];
000058  6801              LDR      r1,[r0,#0]
00005a  1c49              ADDS     r1,r1,#1
00005c  008a              LSLS     r2,r1,#2
00005e  f1a242c0          SUB      r2,r2,#0x60000000
000062  6811              LDR      r1,[r2,#0]
;;;216    
;;;217      /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
;;;218      tmpbtr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \
000064  f0014440          AND      r4,r1,#0xc0000000
;;;219                           FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \
;;;220                           FSMC_BTR1_ACCMOD));
;;;221    					   
;;;222      /* Bank1 NOR/SRAM timing register configuration */
;;;223      tmpbtr |= (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
000068  6b41              LDR      r1,[r0,#0x34]
00006a  e9d13500          LDRD     r3,r5,[r1,#0]
00006e  ea431305          ORR      r3,r3,r5,LSL #4
000072  688d              LDR      r5,[r1,#8]
000074  898e              LDRH     r6,[r1,#0xc]
000076  022d              LSLS     r5,r5,#8
000078  ea454506          ORR      r5,r5,r6,LSL #16
00007c  432b              ORRS     r3,r3,r5
00007e  8a0d              LDRH     r5,[r1,#0x10]
000080  ea435305          ORR      r3,r3,r5,LSL #20
000084  7d0d              LDRB     r5,[r1,#0x14]
000086  6989              LDR      r1,[r1,#0x18]
000088  ea436305          ORR      r3,r3,r5,LSL #24
00008c  430b              ORRS     r3,r3,r1
00008e  4323              ORRS     r3,r3,r4
;;;224                (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
;;;225                (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
;;;226                (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
;;;227                (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
;;;228                (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
;;;229                 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
;;;230                
;;;231      FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = tmpbtr;
000090  6013              STR      r3,[r2,#0]
;;;232    	
;;;233      /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
;;;234      if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
000092  6ac1              LDR      r1,[r0,#0x2c]
000094  f5b14f80          CMP      r1,#0x4000
000098  d008              BEQ      |L14.172|
;;;235      {
;;;236        assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
;;;237        assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
;;;238        assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
;;;239        assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
;;;240        assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
;;;241        assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
;;;242        
;;;243        /* Get the BWTR register value */
;;;244        tmpbwr = FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank];
;;;245        
;;;246        /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
;;;247        tmpbwr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \
;;;248                               FSMC_BWTR1_BUSTURN | FSMC_BWTR1_CLKDIV | FSMC_BWTR1_DATLAT | \
;;;249                               FSMC_BWTR1_ACCMOD));
;;;250        
;;;251        tmpbwr |= (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
;;;252                           (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
;;;253                           (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
;;;254                           (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
;;;255                           (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
;;;256                            FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
;;;257        
;;;258        FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = tmpbwr;
;;;259      }
;;;260      else
;;;261      {
;;;262        FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
00009a  6800              LDR      r0,[r0,#0]
00009c  f06f4170          MVN      r1,#0xf0000000
0000a0  0080              LSLS     r0,r0,#2
0000a2  f1a040c0          SUB      r0,r0,#0x60000000
0000a6  f8c01104          STR      r1,[r0,#0x104]
;;;263      }
;;;264    }
0000aa  bd70              POP      {r4-r6,pc}
                  |L14.172|
0000ac  6801              LDR      r1,[r0,#0]            ;244
0000ae  0089              LSLS     r1,r1,#2              ;244
0000b0  f1a141c0          SUB      r1,r1,#0x60000000     ;244
0000b4  f8d12104          LDR      r2,[r1,#0x104]        ;244
0000b8  f0024340          AND      r3,r2,#0xc0000000     ;247
0000bc  6b80              LDR      r0,[r0,#0x38]         ;251
0000be  e9d02400          LDRD     r2,r4,[r0,#0]         ;251
0000c2  ea421204          ORR      r2,r2,r4,LSL #4       ;251
0000c6  6884              LDR      r4,[r0,#8]            ;251
0000c8  8a05              LDRH     r5,[r0,#0x10]         ;251
0000ca  0224              LSLS     r4,r4,#8              ;251
0000cc  ea445405          ORR      r4,r4,r5,LSL #20      ;251
0000d0  4322              ORRS     r2,r2,r4              ;251
0000d2  7d04              LDRB     r4,[r0,#0x14]         ;251
0000d4  6980              LDR      r0,[r0,#0x18]         ;251
0000d6  ea426204          ORR      r2,r2,r4,LSL #24      ;251
0000da  4302              ORRS     r2,r2,r0              ;251
0000dc  431a              ORRS     r2,r2,r3              ;251
0000de  f8c12104          STR      r2,[r1,#0x104]        ;258
0000e2  bd70              POP      {r4-r6,pc}
;;;265    
                          ENDP

                  |L14.228|
                          DCD      0xfff70080

                          AREA ||i.FSMC_NORSRAMStructInit||, CODE, READONLY, ALIGN=2

                  FSMC_NORSRAMStructInit PROC
;;;271      */
;;;272    void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
000000  2100              MOVS     r1,#0
;;;273    {  
;;;274      /* Reset NOR/SRAM Init structure parameters values */
;;;275      FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
000002  6001              STR      r1,[r0,#0]
;;;276      FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
000004  2202              MOVS     r2,#2
000006  6042              STR      r2,[r0,#4]
;;;277      FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
000008  6081              STR      r1,[r0,#8]
;;;278      FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
00000a  60c1              STR      r1,[r0,#0xc]
;;;279      FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
00000c  6101              STR      r1,[r0,#0x10]
;;;280      FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
00000e  6141              STR      r1,[r0,#0x14]
;;;281      FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
000010  6181              STR      r1,[r0,#0x18]
;;;282      FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
000012  61c1              STR      r1,[r0,#0x1c]
;;;283      FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
000014  6201              STR      r1,[r0,#0x20]
;;;284      FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
000016  02d2              LSLS     r2,r2,#11
000018  6242              STR      r2,[r0,#0x24]
;;;285      FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
00001a  0052              LSLS     r2,r2,#1
00001c  6282              STR      r2,[r0,#0x28]
;;;286      FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
00001e  62c1              STR      r1,[r0,#0x2c]
;;;287      FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
000020  6301              STR      r1,[r0,#0x30]
;;;288      FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef*)&FSMC_DefaultTimingStruct;
000022  4902              LDR      r1,|L15.44|
000024  6341              STR      r1,[r0,#0x34]
;;;289      FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef*)&FSMC_DefaultTimingStruct;
000026  6381              STR      r1,[r0,#0x38]
;;;290    }
000028  4770              BX       lr
;;;291    
                          ENDP

00002a  0000              DCW      0x0000
                  |L15.44|
                          DCD      ||.constdata||

                          AREA ||i.FSMC_PCCARDCmd||, CODE, READONLY, ALIGN=2

                  FSMC_PCCARDCmd PROC
;;;822      */
;;;823    void FSMC_PCCARDCmd(FunctionalState NewState)
000000  f04f4120          MOV      r1,#0xa0000000
;;;824    {
;;;825      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;826      
;;;827      if (NewState != DISABLE)
000004  2800              CMP      r0,#0
000006  d005              BEQ      |L16.20|
;;;828      {
;;;829        /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
;;;830        FSMC_Bank4->PCR4 |= PCR_PBKEN_SET;
000008  f8510fa0          LDR      r0,[r1,#0xa0]!
00000c  f0400004          ORR      r0,r0,#4
000010  6008              STR      r0,[r1,#0]
;;;831      }
;;;832      else
;;;833      {
;;;834        /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
;;;835        FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET;
;;;836      }
;;;837    }
000012  4770              BX       lr
                  |L16.20|
000014  f8510fa0          LDR      r0,[r1,#0xa0]!        ;835
000018  4a01              LDR      r2,|L16.32|
00001a  4010              ANDS     r0,r0,r2              ;835
00001c  6008              STR      r0,[r1,#0]            ;835
00001e  4770              BX       lr
;;;838    /**
                          ENDP

                  |L16.32|
                          DCD      0x000ffffb

                          AREA ||i.FSMC_PCCARDDeInit||, CODE, READONLY, ALIGN=2

                  FSMC_PCCARDDeInit PROC
;;;689      */
;;;690    void FSMC_PCCARDDeInit(void)
000000  4805              LDR      r0,|L17.24|
;;;691    {
;;;692      /* Set the FSMC_Bank4 registers to their reset values */
;;;693      FSMC_Bank4->PCR4 = 0x00000018; 
000002  2118              MOVS     r1,#0x18
000004  6001              STR      r1,[r0,#0]
;;;694      FSMC_Bank4->SR4 = 0x00000000;	
000006  2100              MOVS     r1,#0
000008  6041              STR      r1,[r0,#4]
;;;695      FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
00000a  f04f31fc          MOV      r1,#0xfcfcfcfc
00000e  6081              STR      r1,[r0,#8]
;;;696      FSMC_Bank4->PATT4 = 0xFCFCFCFC;
000010  60c1              STR      r1,[r0,#0xc]
;;;697      FSMC_Bank4->PIO4 = 0xFCFCFCFC;
000012  6101              STR      r1,[r0,#0x10]
;;;698    }
000014  4770              BX       lr
;;;699    
                          ENDP

000016  0000              DCW      0x0000
                  |L17.24|
                          DCD      0xa00000a0

                          AREA ||i.FSMC_PCCARDInit||, CODE, READONLY, ALIGN=2

                  FSMC_PCCARDInit PROC
;;;706      */
;;;707    void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
000000  b510              PUSH     {r4,lr}
;;;708    {
;;;709       uint32_t tmppcr4 = 0, tmppmem4 = 0, tmppatt4 = 0, tmppio4 = 0;
;;;710    
;;;711      /* Check the parameters */
;;;712      assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
;;;713      assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
;;;714      assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
;;;715     
;;;716      assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
;;;717      assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
;;;718      assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
;;;719      assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
;;;720      
;;;721      assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
;;;722      assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
;;;723      assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
;;;724      assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
;;;725      assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
;;;726      assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
;;;727      assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
;;;728      assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
;;;729      
;;;730      /* Get PCCARD control register value */
;;;731      tmppcr4 = FSMC_Bank4->PCR4;
000002  491b              LDR      r1,|L18.112|
000004  680a              LDR      r2,[r1,#0]
;;;732      
;;;733      /* Clear TAR, TCLR, PWAITEN and PWID bits */
;;;734      tmppcr4 &= ((uint32_t)~(FSMC_PCR4_TAR  | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
000006  4b1b              LDR      r3,|L18.116|
000008  401a              ANDS     r2,r2,r3
;;;735                              FSMC_PCR4_PWID));
;;;736    					   
;;;737      /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
;;;738      tmppcr4 |= (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
00000a  6843              LDR      r3,[r0,#4]
00000c  6884              LDR      r4,[r0,#8]
00000e  025b              LSLS     r3,r3,#9
000010  ea433344          ORR      r3,r3,r4,LSL #13
000014  6804              LDR      r4,[r0,#0]
000016  4314              ORRS     r4,r4,r2
000018  4323              ORRS     r3,r3,r4
00001a  f0430210          ORR      r2,r3,#0x10
;;;739                           FSMC_MemoryDataWidth_16b |  
;;;740                           (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
;;;741                           (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
;;;742      
;;;743      FSMC_Bank4->PCR4 = tmppcr4;
00001e  600a              STR      r2,[r1,#0]
;;;744      
;;;745      /* Get PCCARD common space timing register value */
;;;746      tmppmem4 = FSMC_Bank4->PMEM4;
000020  688a              LDR      r2,[r1,#8]
;;;747      
;;;748      /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
;;;749      tmppmem4 &= ((uint32_t)~(FSMC_PMEM4_MEMSET4  | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
;;;750                               FSMC_PMEM4_MEMHIZ4));
;;;751    					   
;;;752      /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
;;;753      tmppmem4 |= (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
000022  68c2              LDR      r2,[r0,#0xc]
000024  e9d23400          LDRD     r3,r4,[r2,#0]
000028  ea432304          ORR      r3,r3,r4,LSL #8
00002c  8914              LDRH     r4,[r2,#8]
00002e  7b12              LDRB     r2,[r2,#0xc]
000030  0424              LSLS     r4,r4,#16
000032  ea446202          ORR      r2,r4,r2,LSL #24
000036  4313              ORRS     r3,r3,r2
;;;754                            (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;755                            (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;756                            (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
;;;757       
;;;758      FSMC_Bank4->PMEM4 = tmppmem4;
000038  608b              STR      r3,[r1,#8]
;;;759      
;;;760      /* Get PCCARD timing parameters */
;;;761      tmppatt4 = FSMC_Bank4->PATT4;
00003a  68ca              LDR      r2,[r1,#0xc]
;;;762    
;;;763      /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
;;;764      tmppatt4 &= ((uint32_t)~(FSMC_PATT4_ATTSET4  | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
;;;765                               FSMC_PATT4_ATTHIZ4));
;;;766    					   
;;;767      /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
;;;768      tmppatt4 |= (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
00003c  6902              LDR      r2,[r0,#0x10]
00003e  e9d23400          LDRD     r3,r4,[r2,#0]
000042  ea432304          ORR      r3,r3,r4,LSL #8
000046  8914              LDRH     r4,[r2,#8]
000048  7b12              LDRB     r2,[r2,#0xc]
00004a  0424              LSLS     r4,r4,#16
00004c  ea446202          ORR      r2,r4,r2,LSL #24
000050  4313              ORRS     r3,r3,r2
;;;769                            (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;770                            (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;771                            (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);	
;;;772       
;;;773      FSMC_Bank4->PATT4 = tmppatt4;
000052  60cb              STR      r3,[r1,#0xc]
;;;774    
;;;775      /* Get FSMC_PCCARD device timing parameters */
;;;776      tmppio4 = FSMC_Bank4->PIO4;
000054  690a              LDR      r2,[r1,#0x10]
;;;777    
;;;778      /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
;;;779      tmppio4 &= ((uint32_t)~(FSMC_PIO4_IOSET4  | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
;;;780                              FSMC_PIO4_IOHIZ4));
;;;781    					   
;;;782      /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
;;;783      tmppio4 |= (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
000056  6940              LDR      r0,[r0,#0x14]
000058  e9d02300          LDRD     r2,r3,[r0,#0]
00005c  ea422203          ORR      r2,r2,r3,LSL #8
000060  8903              LDRH     r3,[r0,#8]
000062  7b00              LDRB     r0,[r0,#0xc]
000064  041b              LSLS     r3,r3,#16
000066  ea436000          ORR      r0,r3,r0,LSL #24
00006a  4302              ORRS     r2,r2,r0
;;;784                           (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;785                           (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;786                           (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
;;;787      
;;;788      FSMC_Bank4->PIO4 = tmppio4;					 
00006c  610a              STR      r2,[r1,#0x10]
;;;789    }
00006e  bd10              POP      {r4,pc}
;;;790    
                          ENDP

                  |L18.112|
                          DCD      0xa00000a0
                  |L18.116|
                          DCD      0xfffe01cd

                          AREA ||i.FSMC_PCCARDStructInit||, CODE, READONLY, ALIGN=1

                  FSMC_PCCARDStructInit PROC
;;;796      */
;;;797    void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
000000  2100              MOVS     r1,#0
;;;798    {
;;;799      /* Reset PCCARD Init structure parameters values */
;;;800      FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
000002  6001              STR      r1,[r0,#0]
;;;801      FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
000004  6041              STR      r1,[r0,#4]
;;;802      FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
000006  6081              STR      r1,[r0,#8]
;;;803      FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
000008  68c2              LDR      r2,[r0,#0xc]
00000a  21fc              MOVS     r1,#0xfc
00000c  6011              STR      r1,[r2,#0]
;;;804      FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00000e  68c2              LDR      r2,[r0,#0xc]
000010  6051              STR      r1,[r2,#4]
;;;805      FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
000012  68c2              LDR      r2,[r0,#0xc]
000014  6091              STR      r1,[r2,#8]
;;;806      FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000016  68c2              LDR      r2,[r0,#0xc]
000018  60d1              STR      r1,[r2,#0xc]
;;;807      FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00001a  6902              LDR      r2,[r0,#0x10]
00001c  6011              STR      r1,[r2,#0]
;;;808      FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00001e  6902              LDR      r2,[r0,#0x10]
000020  6051              STR      r1,[r2,#4]
;;;809      FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
000022  6902              LDR      r2,[r0,#0x10]
000024  6091              STR      r1,[r2,#8]
;;;810      FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;	
000026  6902              LDR      r2,[r0,#0x10]
000028  60d1              STR      r1,[r2,#0xc]
;;;811      FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00002a  6942              LDR      r2,[r0,#0x14]
00002c  6011              STR      r1,[r2,#0]
;;;812      FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00002e  6942              LDR      r2,[r0,#0x14]
000030  6051              STR      r1,[r2,#4]
;;;813      FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
000032  6942              LDR      r2,[r0,#0x14]
000034  6091              STR      r1,[r2,#8]
;;;814      FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000036  6940              LDR      r0,[r0,#0x14]
000038  60c1              STR      r1,[r0,#0xc]
;;;815    }
00003a  4770              BX       lr
;;;816    
                          ENDP


                          AREA ||.constdata||, DATA, READONLY, ALIGN=2

                  FSMC_DefaultTimingStruct
                          DCD      0x0000000f
                          DCD      0x0000000f
                          DCD      0x000000ff
                          DCD      0x0000000f
                          DCD      0x0000000f
                          DCD      0x0000000f
                          DCD      0x00000000

;*** Start embedded assembler ***

#line 1 "..\\..\\Libraries\\STM32F4xx_StdPeriph_Driver\\src\\stm32f4xx_fsmc.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___16_stm32f4xx_fsmc_c_13019877____REV16|
#line 129 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h"
|__asm___16_stm32f4xx_fsmc_c_13019877____REV16| PROC
#line 130

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___16_stm32f4xx_fsmc_c_13019877____REVSH|
#line 144
|__asm___16_stm32f4xx_fsmc_c_13019877____REVSH| PROC
#line 145

 revsh r0, r0
 bx lr
	ENDP
	AREA ||.rrx_text||, CODE
	THUMB
	EXPORT |__asm___16_stm32f4xx_fsmc_c_13019877____RRX|
#line 300
|__asm___16_stm32f4xx_fsmc_c_13019877____RRX| PROC
#line 301

 rrx r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***