stm32f4xx_flash.txt
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; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\flash\obj\stm32f4xx_flash.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\stm32f4xx_flash.d --cpu=Cortex-M4.fp --apcs=interwork -O1 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Include -I..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\uCOS-III\uC-CPU -I..\..\uCOS-III\uC-LIB -I..\..\uCOS-III\uCOS-III\Ports -I..\..\uCOS-III\uCOS-III\Source -I..\..\uCOS-III\uC-CPU\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uC-LIB\Ports\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uCOS-III\Ports\ARM-Cortex-M4\Generic\RealView -I..\..\User -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\libapp -I..\..\RL-ARM\Config -I..\..\RL-ARM\Driver -I..\..\RL-ARM\RL-RTX\inc -I..\..\User\bsp\BSP -I..\..\RL-ARM\RL-CAN -I..\..\Libraries\DSP_LIB\Include -I..\..\MODBUS\modbus\rtu -I..\..\MODBUS\BARE\port -I..\..\MODBUS\modbus\include -I..\..\User\bsp\BSP -I..\..\PLC -I..\..\Avoid -I..\..\User\parameter -I..\..\User\LaserMotionCtr -I..\..\User\W5100S -I..\..\User\bsp -I..\..\User\CHASSIS -I..\..\User\CONTROLFUNCTION -I..\..\User\DATAUPDATE -I..\..\User\HARAWARE -I..\..\User\MOTORDRIVER -I..\..\User\NAVAGATION -I..\..\User\PLATFORM -I..\..\User\SENSOR -I.\RTE\_Flash -IC:\Users\YDJ\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include -IC:\Users\YDJ\AppData\Local\Arm\Packs\Keil\STM32F4xx_DFP\2.13.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include -D__UVISION_VERSION=527 -D_RTE_ -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -D__RTX -D__FPU_USED=1 --omf_browse=.\flash\obj\stm32f4xx_flash.crf ..\..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_flash.c]
THUMB
AREA ||i.FLASH_ClearFlag||, CODE, READONLY, ALIGN=2
FLASH_ClearFlag PROC
;;;1513 */
;;;1514 void FLASH_ClearFlag(uint32_t FLASH_FLAG)
000000 4901 LDR r1,|L1.8|
;;;1515 {
;;;1516 /* Check the parameters */
;;;1517 assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
;;;1518
;;;1519 /* Clear the flags */
;;;1520 FLASH->SR = FLASH_FLAG;
000002 6008 STR r0,[r1,#0]
;;;1521 }
000004 4770 BX lr
;;;1522
ENDP
000006 0000 DCW 0x0000
|L1.8|
DCD 0x40023c0c
AREA ||i.FLASH_DataCacheCmd||, CODE, READONLY, ALIGN=2
FLASH_DataCacheCmd PROC
;;;335 */
;;;336 void FLASH_DataCacheCmd(FunctionalState NewState)
000000 4906 LDR r1,|L2.28|
;;;337 {
;;;338 /* Check the parameters */
;;;339 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;340
;;;341 if(NewState != DISABLE)
000002 2800 CMP r0,#0
000004 d004 BEQ |L2.16|
;;;342 {
;;;343 FLASH->ACR |= FLASH_ACR_DCEN;
000006 6808 LDR r0,[r1,#0]
000008 f4406080 ORR r0,r0,#0x400
00000c 6008 STR r0,[r1,#0]
;;;344 }
;;;345 else
;;;346 {
;;;347 FLASH->ACR &= (~FLASH_ACR_DCEN);
;;;348 }
;;;349 }
00000e 4770 BX lr
|L2.16|
000010 6808 LDR r0,[r1,#0] ;347
000012 f4206080 BIC r0,r0,#0x400 ;347
000016 6008 STR r0,[r1,#0] ;347
000018 4770 BX lr
;;;350
ENDP
00001a 0000 DCW 0x0000
|L2.28|
DCD 0x40023c00
AREA ||i.FLASH_DataCacheReset||, CODE, READONLY, ALIGN=2
FLASH_DataCacheReset PROC
;;;367 */
;;;368 void FLASH_DataCacheReset(void)
000000 4802 LDR r0,|L3.12|
;;;369 {
;;;370 FLASH->ACR |= FLASH_ACR_DCRST;
000002 6801 LDR r1,[r0,#0]
000004 f4415180 ORR r1,r1,#0x1000
000008 6001 STR r1,[r0,#0]
;;;371 }
00000a 4770 BX lr
;;;372
ENDP
|L3.12|
DCD 0x40023c00
AREA ||i.FLASH_EraseAllBank1Sectors||, CODE, READONLY, ALIGN=2
FLASH_EraseAllBank1Sectors PROC
;;;618 */
;;;619 FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
000000 b530 PUSH {r4,r5,lr}
;;;620 {
000002 4604 MOV r4,r0
;;;621 uint32_t tmp_psize = 0x0;
000004 2500 MOVS r5,#0
;;;622 FLASH_Status status = FLASH_COMPLETE;
;;;623
;;;624 /* Wait for last operation to be completed */
;;;625 status = FLASH_WaitForLastOperation();
000006 f7fffffe BL FLASH_WaitForLastOperation
;;;626 assert_param(IS_VOLTAGERANGE(VoltageRange));
;;;627
;;;628 if(VoltageRange == VoltageRange_1)
00000a b12c CBZ r4,|L4.24|
;;;629 {
;;;630 tmp_psize = FLASH_PSIZE_BYTE;
;;;631 }
;;;632 else if(VoltageRange == VoltageRange_2)
00000c 2c01 CMP r4,#1
00000e d01c BEQ |L4.74|
;;;633 {
;;;634 tmp_psize = FLASH_PSIZE_HALF_WORD;
;;;635 }
;;;636 else if(VoltageRange == VoltageRange_3)
000010 2c02 CMP r4,#2
000012 d01d BEQ |L4.80|
;;;637 {
;;;638 tmp_psize = FLASH_PSIZE_WORD;
;;;639 }
;;;640 else
;;;641 {
;;;642 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
000014 f44f7540 MOV r5,#0x300
|L4.24|
;;;643 }
;;;644 if(status == FLASH_COMPLETE)
000018 2809 CMP r0,#9
00001a d115 BNE |L4.72|
;;;645 {
;;;646 /* if the previous operation is completed, proceed to erase all sectors */
;;;647 FLASH->CR &= CR_PSIZE_MASK;
00001c 4c0e LDR r4,|L4.88|
00001e 6820 LDR r0,[r4,#0]
000020 f4207040 BIC r0,r0,#0x300
000024 6020 STR r0,[r4,#0]
;;;648 FLASH->CR |= tmp_psize;
000026 6820 LDR r0,[r4,#0]
000028 4328 ORRS r0,r0,r5
00002a 6020 STR r0,[r4,#0]
;;;649 FLASH->CR |= FLASH_CR_MER1;
00002c 6820 LDR r0,[r4,#0]
00002e f0400004 ORR r0,r0,#4
000032 6020 STR r0,[r4,#0]
;;;650 FLASH->CR |= FLASH_CR_STRT;
000034 6820 LDR r0,[r4,#0]
000036 f4403080 ORR r0,r0,#0x10000
00003a 6020 STR r0,[r4,#0]
;;;651
;;;652 /* Wait for last operation to be completed */
;;;653 status = FLASH_WaitForLastOperation();
00003c f7fffffe BL FLASH_WaitForLastOperation
;;;654
;;;655 /* if the erase operation is completed, disable the MER Bit */
;;;656 FLASH->CR &= (~FLASH_CR_MER1);
000040 6821 LDR r1,[r4,#0]
000042 f0210104 BIC r1,r1,#4
000046 6021 STR r1,[r4,#0]
|L4.72|
;;;657
;;;658 }
;;;659 /* Return the Erase Status */
;;;660 return status;
;;;661 }
000048 bd30 POP {r4,r5,pc}
|L4.74|
00004a f44f7580 MOV r5,#0x100 ;634
00004e e7e3 B |L4.24|
|L4.80|
000050 f44f7500 MOV r5,#0x200 ;638
000054 e7e0 B |L4.24|
;;;662
ENDP
000056 0000 DCW 0x0000
|L4.88|
DCD 0x40023c10
AREA ||i.FLASH_EraseAllBank2Sectors||, CODE, READONLY, ALIGN=2
FLASH_EraseAllBank2Sectors PROC
;;;685 */
;;;686 FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
000000 b530 PUSH {r4,r5,lr}
;;;687 {
000002 4604 MOV r4,r0
;;;688 uint32_t tmp_psize = 0x0;
000004 2500 MOVS r5,#0
;;;689 FLASH_Status status = FLASH_COMPLETE;
;;;690
;;;691 /* Wait for last operation to be completed */
;;;692 status = FLASH_WaitForLastOperation();
000006 f7fffffe BL FLASH_WaitForLastOperation
;;;693 assert_param(IS_VOLTAGERANGE(VoltageRange));
;;;694
;;;695 if(VoltageRange == VoltageRange_1)
00000a b12c CBZ r4,|L5.24|
;;;696 {
;;;697 tmp_psize = FLASH_PSIZE_BYTE;
;;;698 }
;;;699 else if(VoltageRange == VoltageRange_2)
00000c 2c01 CMP r4,#1
00000e d01c BEQ |L5.74|
;;;700 {
;;;701 tmp_psize = FLASH_PSIZE_HALF_WORD;
;;;702 }
;;;703 else if(VoltageRange == VoltageRange_3)
000010 2c02 CMP r4,#2
000012 d01d BEQ |L5.80|
;;;704 {
;;;705 tmp_psize = FLASH_PSIZE_WORD;
;;;706 }
;;;707 else
;;;708 {
;;;709 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
000014 f44f7540 MOV r5,#0x300
|L5.24|
;;;710 }
;;;711 if(status == FLASH_COMPLETE)
000018 2809 CMP r0,#9
00001a d115 BNE |L5.72|
;;;712 {
;;;713 /* if the previous operation is completed, proceed to erase all sectors */
;;;714 FLASH->CR &= CR_PSIZE_MASK;
00001c 4c0e LDR r4,|L5.88|
00001e 6820 LDR r0,[r4,#0]
000020 f4207040 BIC r0,r0,#0x300
000024 6020 STR r0,[r4,#0]
;;;715 FLASH->CR |= tmp_psize;
000026 6820 LDR r0,[r4,#0]
000028 4328 ORRS r0,r0,r5
00002a 6020 STR r0,[r4,#0]
;;;716 FLASH->CR |= FLASH_CR_MER2;
00002c 6820 LDR r0,[r4,#0]
00002e f4404000 ORR r0,r0,#0x8000
000032 6020 STR r0,[r4,#0]
;;;717 FLASH->CR |= FLASH_CR_STRT;
000034 6820 LDR r0,[r4,#0]
000036 f4403080 ORR r0,r0,#0x10000
00003a 6020 STR r0,[r4,#0]
;;;718
;;;719 /* Wait for last operation to be completed */
;;;720 status = FLASH_WaitForLastOperation();
00003c f7fffffe BL FLASH_WaitForLastOperation
;;;721
;;;722 /* if the erase operation is completed, disable the MER Bit */
;;;723 FLASH->CR &= (~FLASH_CR_MER2);
000040 6821 LDR r1,[r4,#0]
000042 f4214100 BIC r1,r1,#0x8000
000046 6021 STR r1,[r4,#0]
|L5.72|
;;;724
;;;725 }
;;;726 /* Return the Erase Status */
;;;727 return status;
;;;728 }
000048 bd30 POP {r4,r5,pc}
|L5.74|
00004a f44f7580 MOV r5,#0x100 ;701
00004e e7e3 B |L5.24|
|L5.80|
000050 f44f7500 MOV r5,#0x200 ;705
000054 e7e0 B |L5.24|
;;;729
ENDP
000056 0000 DCW 0x0000
|L5.88|
DCD 0x40023c10
AREA ||i.FLASH_EraseAllSectors||, CODE, READONLY, ALIGN=2
FLASH_EraseAllSectors PROC
;;;537 */
;;;538 FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
000000 b530 PUSH {r4,r5,lr}
;;;539 {
000002 4604 MOV r4,r0
;;;540 uint32_t tmp_psize = 0x0;
000004 2500 MOVS r5,#0
;;;541 FLASH_Status status = FLASH_COMPLETE;
;;;542
;;;543 /* Wait for last operation to be completed */
;;;544 status = FLASH_WaitForLastOperation();
000006 f7fffffe BL FLASH_WaitForLastOperation
;;;545 assert_param(IS_VOLTAGERANGE(VoltageRange));
;;;546
;;;547 if(VoltageRange == VoltageRange_1)
00000a b12c CBZ r4,|L6.24|
;;;548 {
;;;549 tmp_psize = FLASH_PSIZE_BYTE;
;;;550 }
;;;551 else if(VoltageRange == VoltageRange_2)
00000c 2c01 CMP r4,#1
00000e d01c BEQ |L6.74|
;;;552 {
;;;553 tmp_psize = FLASH_PSIZE_HALF_WORD;
;;;554 }
;;;555 else if(VoltageRange == VoltageRange_3)
000010 2c02 CMP r4,#2
000012 d01d BEQ |L6.80|
;;;556 {
;;;557 tmp_psize = FLASH_PSIZE_WORD;
;;;558 }
;;;559 else
;;;560 {
;;;561 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
000014 f44f7540 MOV r5,#0x300
|L6.24|
;;;562 }
;;;563 if(status == FLASH_COMPLETE)
000018 2809 CMP r0,#9
00001a d115 BNE |L6.72|
;;;564 {
;;;565 /* if the previous operation is completed, proceed to erase all sectors */
;;;566 #if defined(STM32F427_437xx) || defined(STM32F429_439xx)
;;;567 FLASH->CR &= CR_PSIZE_MASK;
;;;568 FLASH->CR |= tmp_psize;
;;;569 FLASH->CR |= (FLASH_CR_MER1 | FLASH_CR_MER2);
;;;570 FLASH->CR |= FLASH_CR_STRT;
;;;571
;;;572 /* Wait for last operation to be completed */
;;;573 status = FLASH_WaitForLastOperation();
;;;574
;;;575 /* if the erase operation is completed, disable the MER Bit */
;;;576 FLASH->CR &= ~(FLASH_CR_MER1 | FLASH_CR_MER2);
;;;577 #endif /* STM32F427_437xx || STM32F429_439xx */
;;;578
;;;579 #if defined(STM32F40_41xxx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F446xx)
;;;580 FLASH->CR &= CR_PSIZE_MASK;
00001c 4c0e LDR r4,|L6.88|
00001e 6820 LDR r0,[r4,#0]
000020 f4207040 BIC r0,r0,#0x300
000024 6020 STR r0,[r4,#0]
;;;581 FLASH->CR |= tmp_psize;
000026 6820 LDR r0,[r4,#0]
000028 4328 ORRS r0,r0,r5
00002a 6020 STR r0,[r4,#0]
;;;582 FLASH->CR |= FLASH_CR_MER;
00002c 6820 LDR r0,[r4,#0]
00002e f0400004 ORR r0,r0,#4
000032 6020 STR r0,[r4,#0]
;;;583 FLASH->CR |= FLASH_CR_STRT;
000034 6820 LDR r0,[r4,#0]
000036 f4403080 ORR r0,r0,#0x10000
00003a 6020 STR r0,[r4,#0]
;;;584
;;;585 /* Wait for last operation to be completed */
;;;586 status = FLASH_WaitForLastOperation();
00003c f7fffffe BL FLASH_WaitForLastOperation
;;;587
;;;588 /* if the erase operation is completed, disable the MER Bit */
;;;589 FLASH->CR &= (~FLASH_CR_MER);
000040 6821 LDR r1,[r4,#0]
000042 f0210104 BIC r1,r1,#4
000046 6021 STR r1,[r4,#0]
|L6.72|
;;;590 #endif /* STM32F40_41xxx || STM32F401xx || STM32F411xE || STM32F446xx */
;;;591
;;;592 }
;;;593 /* Return the Erase Status */
;;;594 return status;
;;;595 }
000048 bd30 POP {r4,r5,pc}
|L6.74|
00004a f44f7580 MOV r5,#0x100 ;553
00004e e7e3 B |L6.24|
|L6.80|
000050 f44f7500 MOV r5,#0x200 ;557
000054 e7e0 B |L6.24|
;;;596
ENDP
000056 0000 DCW 0x0000
|L6.88|
DCD 0x40023c10
AREA ||i.FLASH_EraseSector||, CODE, READONLY, ALIGN=2
FLASH_EraseSector PROC
;;;469 */
;;;470 FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
000000 b570 PUSH {r4-r6,lr}
;;;471 {
000002 4606 MOV r6,r0
;;;472 uint32_t tmp_psize = 0x0;
000004 2500 MOVS r5,#0
;;;473 FLASH_Status status = FLASH_COMPLETE;
;;;474
;;;475 /* Check the parameters */
;;;476 assert_param(IS_FLASH_SECTOR(FLASH_Sector));
;;;477 assert_param(IS_VOLTAGERANGE(VoltageRange));
;;;478
;;;479 if(VoltageRange == VoltageRange_1)
000006 2900 CMP r1,#0
000008 d005 BEQ |L7.22|
;;;480 {
;;;481 tmp_psize = FLASH_PSIZE_BYTE;
;;;482 }
;;;483 else if(VoltageRange == VoltageRange_2)
00000a 2901 CMP r1,#1
00000c d027 BEQ |L7.94|
;;;484 {
;;;485 tmp_psize = FLASH_PSIZE_HALF_WORD;
;;;486 }
;;;487 else if(VoltageRange == VoltageRange_3)
00000e 2902 CMP r1,#2
000010 d028 BEQ |L7.100|
;;;488 {
;;;489 tmp_psize = FLASH_PSIZE_WORD;
;;;490 }
;;;491 else
;;;492 {
;;;493 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
000012 f44f7540 MOV r5,#0x300
|L7.22|
;;;494 }
;;;495 /* Wait for last operation to be completed */
;;;496 status = FLASH_WaitForLastOperation();
000016 f7fffffe BL FLASH_WaitForLastOperation
;;;497
;;;498 if(status == FLASH_COMPLETE)
00001a 2809 CMP r0,#9
00001c d11e BNE |L7.92|
;;;499 {
;;;500 /* if the previous operation is completed, proceed to erase the sector */
;;;501 FLASH->CR &= CR_PSIZE_MASK;
00001e 4c13 LDR r4,|L7.108|
000020 6820 LDR r0,[r4,#0]
000022 f4207040 BIC r0,r0,#0x300
000026 6020 STR r0,[r4,#0]
;;;502 FLASH->CR |= tmp_psize;
000028 6820 LDR r0,[r4,#0]
00002a 4328 ORRS r0,r0,r5
00002c 6020 STR r0,[r4,#0]
;;;503 FLASH->CR &= SECTOR_MASK;
00002e 6820 LDR r0,[r4,#0]
000030 f02000f8 BIC r0,r0,#0xf8
000034 6020 STR r0,[r4,#0]
;;;504 FLASH->CR |= FLASH_CR_SER | FLASH_Sector;
000036 6820 LDR r0,[r4,#0]
000038 f0460102 ORR r1,r6,#2
00003c 4308 ORRS r0,r0,r1
00003e 6020 STR r0,[r4,#0]
;;;505 FLASH->CR |= FLASH_CR_STRT;
000040 6820 LDR r0,[r4,#0]
000042 f4403080 ORR r0,r0,#0x10000
000046 6020 STR r0,[r4,#0]
;;;506
;;;507 /* Wait for last operation to be completed */
;;;508 status = FLASH_WaitForLastOperation();
000048 f7fffffe BL FLASH_WaitForLastOperation
;;;509
;;;510 /* if the erase operation is completed, disable the SER Bit */
;;;511 FLASH->CR &= (~FLASH_CR_SER);
00004c 6821 LDR r1,[r4,#0]
00004e f0210102 BIC r1,r1,#2
000052 6021 STR r1,[r4,#0]
;;;512 FLASH->CR &= SECTOR_MASK;
000054 6821 LDR r1,[r4,#0]
000056 f02101f8 BIC r1,r1,#0xf8
00005a 6021 STR r1,[r4,#0]
|L7.92|
;;;513 }
;;;514 /* Return the Erase Status */
;;;515 return status;
;;;516 }
00005c bd70 POP {r4-r6,pc}
|L7.94|
00005e f44f7580 MOV r5,#0x100 ;485
000062 e7d8 B |L7.22|
|L7.100|
000064 f44f7500 MOV r5,#0x200 ;489
000068 e7d5 B |L7.22|
;;;517
ENDP
00006a 0000 DCW 0x0000
|L7.108|
DCD 0x40023c10
AREA ||i.FLASH_GetFlagStatus||, CODE, READONLY, ALIGN=2
FLASH_GetFlagStatus PROC
;;;1482 */
;;;1483 FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
000000 4601 MOV r1,r0
;;;1484 {
;;;1485 FlagStatus bitstatus = RESET;
000002 2000 MOVS r0,#0
;;;1486 /* Check the parameters */
;;;1487 assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
;;;1488
;;;1489 if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
000004 4a02 LDR r2,|L8.16|
000006 6812 LDR r2,[r2,#0]
000008 420a TST r2,r1
00000a d000 BEQ |L8.14|
;;;1490 {
;;;1491 bitstatus = SET;
00000c 2001 MOVS r0,#1
|L8.14|
;;;1492 }
;;;1493 else
;;;1494 {
;;;1495 bitstatus = RESET;
;;;1496 }
;;;1497 /* Return the new state of FLASH_FLAG (SET or RESET) */
;;;1498 return bitstatus;
;;;1499 }
00000e 4770 BX lr
;;;1500
ENDP
|L8.16|
DCD 0x40023c0c
AREA ||i.FLASH_GetStatus||, CODE, READONLY, ALIGN=2
FLASH_GetStatus PROC
;;;1528 */
;;;1529 FLASH_Status FLASH_GetStatus(void)
000000 2009 MOVS r0,#9
;;;1530 {
;;;1531 FLASH_Status flashstatus = FLASH_COMPLETE;
;;;1532
;;;1533 if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
000002 490d LDR r1,|L9.56|
000004 680a LDR r2,[r1,#0]
000006 03d2 LSLS r2,r2,#15
000008 d501 BPL |L9.14|
;;;1534 {
;;;1535 flashstatus = FLASH_BUSY;
00000a 2001 MOVS r0,#1
;;;1536 }
;;;1537 else
;;;1538 {
;;;1539 if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00)
;;;1540 {
;;;1541 flashstatus = FLASH_ERROR_WRP;
;;;1542 }
;;;1543 else
;;;1544 {
;;;1545 if((FLASH->SR & FLASH_FLAG_RDERR) != (uint32_t)0x00)
;;;1546 {
;;;1547 flashstatus = FLASH_ERROR_RD;
;;;1548 }
;;;1549 else
;;;1550 {
;;;1551 if((FLASH->SR & (uint32_t)0xE0) != (uint32_t)0x00)
;;;1552 {
;;;1553 flashstatus = FLASH_ERROR_PROGRAM;
;;;1554 }
;;;1555 else
;;;1556 {
;;;1557 if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00)
;;;1558 {
;;;1559 flashstatus = FLASH_ERROR_OPERATION;
;;;1560 }
;;;1561 else
;;;1562 {
;;;1563 flashstatus = FLASH_COMPLETE;
;;;1564 }
;;;1565 }
;;;1566 }
;;;1567 }
;;;1568 }
;;;1569 /* Return the FLASH Status */
;;;1570 return flashstatus;
;;;1571 }
00000c 4770 BX lr
|L9.14|
00000e 680a LDR r2,[r1,#0] ;1539
000010 06d2 LSLS r2,r2,#27 ;1539
000012 d501 BPL |L9.24|
000014 2006 MOVS r0,#6 ;1541
000016 4770 BX lr
|L9.24|
000018 680a LDR r2,[r1,#0] ;1545
00001a 05d2 LSLS r2,r2,#23 ;1545
00001c d501 BPL |L9.34|
00001e 2002 MOVS r0,#2 ;1547
000020 4770 BX lr
|L9.34|
000022 680a LDR r2,[r1,#0] ;1551
000024 f0120fe0 TST r2,#0xe0 ;1551
000028 d001 BEQ |L9.46|
00002a 2007 MOVS r0,#7 ;1553
|L9.44|
00002c 4770 BX lr
|L9.46|
00002e 6809 LDR r1,[r1,#0] ;1557
000030 0789 LSLS r1,r1,#30 ;1557
000032 d5fb BPL |L9.44|
000034 2008 MOVS r0,#8 ;1559
000036 4770 BX lr
;;;1572
ENDP
|L9.56|
DCD 0x40023c0c
AREA ||i.FLASH_ITConfig||, CODE, READONLY, ALIGN=2
FLASH_ITConfig PROC
;;;1450 */
;;;1451 void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
000000 4a05 LDR r2,|L10.24|
;;;1452 {
;;;1453 /* Check the parameters */
;;;1454 assert_param(IS_FLASH_IT(FLASH_IT));
;;;1455 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1456
;;;1457 if(NewState != DISABLE)
000002 2900 CMP r1,#0
000004 d003 BEQ |L10.14|
;;;1458 {
;;;1459 /* Enable the interrupt sources */
;;;1460 FLASH->CR |= FLASH_IT;
000006 6811 LDR r1,[r2,#0]
000008 4301 ORRS r1,r1,r0
00000a 6011 STR r1,[r2,#0]
;;;1461 }
;;;1462 else
;;;1463 {
;;;1464 /* Disable the interrupt sources */
;;;1465 FLASH->CR &= ~(uint32_t)FLASH_IT;
;;;1466 }
;;;1467 }
00000c 4770 BX lr
|L10.14|
00000e 6811 LDR r1,[r2,#0] ;1465
000010 4381 BICS r1,r1,r0 ;1465
000012 6011 STR r1,[r2,#0] ;1465
000014 4770 BX lr
;;;1468
ENDP
000016 0000 DCW 0x0000
|L10.24|
DCD 0x40023c10
AREA ||i.FLASH_InstructionCacheCmd||, CODE, READONLY, ALIGN=2
FLASH_InstructionCacheCmd PROC
;;;314 */
;;;315 void FLASH_InstructionCacheCmd(FunctionalState NewState)
000000 4906 LDR r1,|L11.28|
;;;316 {
;;;317 /* Check the parameters */
;;;318 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;319
;;;320 if(NewState != DISABLE)
000002 2800 CMP r0,#0
000004 d004 BEQ |L11.16|
;;;321 {
;;;322 FLASH->ACR |= FLASH_ACR_ICEN;
000006 6808 LDR r0,[r1,#0]
000008 f4407000 ORR r0,r0,#0x200
00000c 6008 STR r0,[r1,#0]
;;;323 }
;;;324 else
;;;325 {
;;;326 FLASH->ACR &= (~FLASH_ACR_ICEN);
;;;327 }
;;;328 }
00000e 4770 BX lr
|L11.16|
000010 6808 LDR r0,[r1,#0] ;326
000012 f4207000 BIC r0,r0,#0x200 ;326
000016 6008 STR r0,[r1,#0] ;326
000018 4770 BX lr
;;;329
ENDP
00001a 0000 DCW 0x0000
|L11.28|
DCD 0x40023c00
AREA ||i.FLASH_InstructionCacheReset||, CODE, READONLY, ALIGN=2
FLASH_InstructionCacheReset PROC
;;;356 */
;;;357 void FLASH_InstructionCacheReset(void)
000000 4802 LDR r0,|L12.12|
;;;358 {
;;;359 FLASH->ACR |= FLASH_ACR_ICRST;
000002 6801 LDR r1,[r0,#0]
000004 f4416100 ORR r1,r1,#0x800
000008 6001 STR r1,[r0,#0]
;;;360 }
00000a 4770 BX lr
;;;361
ENDP
|L12.12|
DCD 0x40023c00
AREA ||i.FLASH_Lock||, CODE, READONLY, ALIGN=2
FLASH_Lock PROC
;;;429 */
;;;430 void FLASH_Lock(void)
000000 4802 LDR r0,|L13.12|
;;;431 {
;;;432 /* Set the LOCK Bit to lock the FLASH Registers access */
;;;433 FLASH->CR |= FLASH_CR_LOCK;
000002 6801 LDR r1,[r0,#0]
000004 f0414100 ORR r1,r1,#0x80000000
000008 6001 STR r1,[r0,#0]
;;;434 }
00000a 4770 BX lr
;;;435
ENDP
|L13.12|
DCD 0x40023c10
AREA ||i.FLASH_OB_BORConfig||, CODE, READONLY, ALIGN=2
FLASH_OB_BORConfig PROC
;;;1295 */
;;;1296 void FLASH_OB_BORConfig(uint8_t OB_BOR)
000000 4904 LDR r1,|L14.20|
;;;1297 {
;;;1298 /* Check the parameters */
;;;1299 assert_param(IS_OB_BOR(OB_BOR));
;;;1300
;;;1301 /* Set the BOR Level */
;;;1302 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
000002 780a LDRB r2,[r1,#0]
000004 f022020c BIC r2,r2,#0xc
000008 700a STRB r2,[r1,#0]
;;;1303 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR;
00000a 780a LDRB r2,[r1,#0]
00000c 4302 ORRS r2,r2,r0
00000e 700a STRB r2,[r1,#0]
;;;1304
;;;1305 }
000010 4770 BX lr
;;;1306
ENDP
000012 0000 DCW 0x0000
|L14.20|
DCD 0x40023c14
AREA ||i.FLASH_OB_BootConfig||, CODE, READONLY, ALIGN=2
FLASH_OB_BootConfig PROC
;;;1274 */
;;;1275 void FLASH_OB_BootConfig(uint8_t OB_BOOT)
000000 4904 LDR r1,|L15.20|
;;;1276 {
;;;1277 /* Check the parameters */
;;;1278 assert_param(IS_OB_BOOT(OB_BOOT));
;;;1279
;;;1280 /* Set Dual Bank Boot */
;;;1281 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);
000002 780a LDRB r2,[r1,#0]
000004 f0220210 BIC r2,r2,#0x10
000008 700a STRB r2,[r1,#0]
;;;1282 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOOT;
00000a 780a LDRB r2,[r1,#0]
00000c 4302 ORRS r2,r2,r0
00000e 700a STRB r2,[r1,#0]
;;;1283
;;;1284 }
000010 4770 BX lr
;;;1285
ENDP
000012 0000 DCW 0x0000
|L15.20|
DCD 0x40023c14
AREA ||i.FLASH_OB_GetBOR||, CODE, READONLY, ALIGN=2
FLASH_OB_GetBOR PROC
;;;1421 */
;;;1422 uint8_t FLASH_OB_GetBOR(void)
000000 4802 LDR r0,|L16.12|
;;;1423 {
;;;1424 /* Return the FLASH BOR level */
;;;1425 return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
000002 7800 LDRB r0,[r0,#0]
000004 f000000c AND r0,r0,#0xc
;;;1426 }
000008 4770 BX lr
;;;1427
ENDP
00000a 0000 DCW 0x0000
|L16.12|
DCD 0x40023c14
AREA ||i.FLASH_OB_GetPCROP||, CODE, READONLY, ALIGN=2
FLASH_OB_GetPCROP PROC
;;;1370 */
;;;1371 uint16_t FLASH_OB_GetPCROP(void)
000000 4801 LDR r0,|L17.8|
;;;1372 {
;;;1373 /* Return the FLASH PC Read/write protection Register value */
;;;1374 return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
000002 8800 LDRH r0,[r0,#0]
;;;1375 }
000004 4770 BX lr
;;;1376
ENDP
000006 0000 DCW 0x0000
|L17.8|
DCD 0x40023c16
AREA ||i.FLASH_OB_GetPCROP1||, CODE, READONLY, ALIGN=2
FLASH_OB_GetPCROP1 PROC
;;;1384 */
;;;1385 uint16_t FLASH_OB_GetPCROP1(void)
000000 4801 LDR r0,|L18.8|
;;;1386 {
;;;1387 /* Return the FLASH write protection Register value */
;;;1388 return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
000002 8800 LDRH r0,[r0,#0]
;;;1389 }
000004 4770 BX lr
;;;1390
ENDP
000006 0000 DCW 0x0000
|L18.8|
DCD 0x40023c1a
AREA ||i.FLASH_OB_GetRDP||, CODE, READONLY, ALIGN=2
FLASH_OB_GetRDP PROC
;;;1397 */
;;;1398 FlagStatus FLASH_OB_GetRDP(void)
000000 2000 MOVS r0,#0
;;;1399 {
;;;1400 FlagStatus readstatus = RESET;
;;;1401
;;;1402 if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0))
000002 4903 LDR r1,|L19.16|
000004 7809 LDRB r1,[r1,#0]
000006 29aa CMP r1,#0xaa
000008 d000 BEQ |L19.12|
;;;1403 {
;;;1404 readstatus = SET;
00000a 2001 MOVS r0,#1
|L19.12|
;;;1405 }
;;;1406 else
;;;1407 {
;;;1408 readstatus = RESET;
;;;1409 }
;;;1410 return readstatus;
;;;1411 }
00000c 4770 BX lr
;;;1412
ENDP
00000e 0000 DCW 0x0000
|L19.16|
DCD 0x40023c15
AREA ||i.FLASH_OB_GetUser||, CODE, READONLY, ALIGN=2
FLASH_OB_GetUser PROC
;;;1331 */
;;;1332 uint8_t FLASH_OB_GetUser(void)
000000 4802 LDR r0,|L20.12|
;;;1333 {
;;;1334 /* Return the User Option Byte */
;;;1335 return (uint8_t)(FLASH->OPTCR >> 5);
000002 6800 LDR r0,[r0,#0]
000004 f3c01047 UBFX r0,r0,#5,#8
;;;1336 }
000008 4770 BX lr
;;;1337
ENDP
00000a 0000 DCW 0x0000
|L20.12|
DCD 0x40023c14
AREA ||i.FLASH_OB_GetWRP||, CODE, READONLY, ALIGN=2
FLASH_OB_GetWRP PROC
;;;1342 */
;;;1343 uint16_t FLASH_OB_GetWRP(void)
000000 4801 LDR r0,|L21.8|
;;;1344 {
;;;1345 /* Return the FLASH write protection Register value */
;;;1346 return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
000002 8800 LDRH r0,[r0,#0]
;;;1347 }
000004 4770 BX lr
;;;1348
ENDP
000006 0000 DCW 0x0000
|L21.8|
DCD 0x40023c16
AREA ||i.FLASH_OB_GetWRP1||, CODE, READONLY, ALIGN=2
FLASH_OB_GetWRP1 PROC
;;;1356 */
;;;1357 uint16_t FLASH_OB_GetWRP1(void)
000000 4801 LDR r0,|L22.8|
;;;1358 {
;;;1359 /* Return the FLASH write protection Register value */
;;;1360 return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
000002 8800 LDRH r0,[r0,#0]
;;;1361 }
000004 4770 BX lr
;;;1362
ENDP
000006 0000 DCW 0x0000
|L22.8|
DCD 0x40023c1a
AREA ||i.FLASH_OB_Launch||, CODE, READONLY, ALIGN=2
FLASH_OB_Launch PROC
;;;1312 */
;;;1313 FLASH_Status FLASH_OB_Launch(void)
000000 4803 LDR r0,|L23.16|
;;;1314 {
;;;1315 FLASH_Status status = FLASH_COMPLETE;
;;;1316
;;;1317 /* Set the OPTSTRT bit in OPTCR register */
;;;1318 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
000002 7801 LDRB r1,[r0,#0]
000004 f0410102 ORR r1,r1,#2
000008 7001 STRB r1,[r0,#0]
;;;1319
;;;1320 /* Wait for last operation to be completed */
;;;1321 status = FLASH_WaitForLastOperation();
00000a f7ffbffe B.W FLASH_WaitForLastOperation
;;;1322
;;;1323 return status;
;;;1324 }
;;;1325
ENDP
00000e 0000 DCW 0x0000
|L23.16|
DCD 0x40023c14
AREA ||i.FLASH_OB_Lock||, CODE, READONLY, ALIGN=2
FLASH_OB_Lock PROC
;;;983 */
;;;984 void FLASH_OB_Lock(void)
000000 4802 LDR r0,|L24.12|
;;;985 {
;;;986 /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
;;;987 FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
000002 6801 LDR r1,[r0,#0]
000004 f0410101 ORR r1,r1,#1
000008 6001 STR r1,[r0,#0]
;;;988 }
00000a 4770 BX lr
;;;989
ENDP
|L24.12|
DCD 0x40023c14
AREA ||i.FLASH_OB_PCROP1Config||, CODE, READONLY, ALIGN=2
FLASH_OB_PCROP1Config PROC
;;;1165 */
;;;1166 void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
000000 b530 PUSH {r4,r5,lr}
;;;1167 {
000002 4604 MOV r4,r0
000004 460d MOV r5,r1
;;;1168 FLASH_Status status = FLASH_COMPLETE;
;;;1169
;;;1170 /* Check the parameters */
;;;1171 assert_param(IS_OB_PCROP(OB_PCROP));
;;;1172 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1173
;;;1174 status = FLASH_WaitForLastOperation();
000006 f7fffffe BL FLASH_WaitForLastOperation
;;;1175
;;;1176 if(status == FLASH_COMPLETE)
00000a 2809 CMP r0,#9
00000c d104 BNE |L25.24|
;;;1177 {
;;;1178 if(NewState != DISABLE)
;;;1179 {
;;;1180 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_PCROP;
00000e 4805 LDR r0,|L25.36|
000010 b11d CBZ r5,|L25.26|
000012 8801 LDRH r1,[r0,#0]
000014 4321 ORRS r1,r1,r4
000016 8001 STRH r1,[r0,#0]
|L25.24|
;;;1181 }
;;;1182 else
;;;1183 {
;;;1184 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_PCROP);
;;;1185 }
;;;1186 }
;;;1187 }
000018 bd30 POP {r4,r5,pc}
|L25.26|
00001a 8801 LDRH r1,[r0,#0] ;1184
00001c 43a1 BICS r1,r1,r4 ;1184
00001e 8001 STRH r1,[r0,#0] ;1184
000020 bd30 POP {r4,r5,pc}
;;;1188
ENDP
000022 0000 DCW 0x0000
|L25.36|
DCD 0x40023c1a
AREA ||i.FLASH_OB_PCROPConfig||, CODE, READONLY, ALIGN=2
FLASH_OB_PCROPConfig PROC
;;;1128 */
;;;1129 void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
000000 b530 PUSH {r4,r5,lr}
;;;1130 {
000002 4604 MOV r4,r0
000004 460d MOV r5,r1
;;;1131 FLASH_Status status = FLASH_COMPLETE;
;;;1132
;;;1133 /* Check the parameters */
;;;1134 assert_param(IS_OB_PCROP(OB_PCROP));
;;;1135 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1136
;;;1137 status = FLASH_WaitForLastOperation();
000006 f7fffffe BL FLASH_WaitForLastOperation
;;;1138
;;;1139 if(status == FLASH_COMPLETE)
00000a 2809 CMP r0,#9
00000c d104 BNE |L26.24|
;;;1140 {
;;;1141 if(NewState != DISABLE)
;;;1142 {
;;;1143 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_PCROP;
00000e 4805 LDR r0,|L26.36|
000010 b11d CBZ r5,|L26.26|
000012 8801 LDRH r1,[r0,#0]
000014 4321 ORRS r1,r1,r4
000016 8001 STRH r1,[r0,#0]
|L26.24|
;;;1144 }
;;;1145 else
;;;1146 {
;;;1147 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_PCROP);
;;;1148 }
;;;1149 }
;;;1150 }
000018 bd30 POP {r4,r5,pc}
|L26.26|
00001a 8801 LDRH r1,[r0,#0] ;1147
00001c 43a1 BICS r1,r1,r4 ;1147
00001e 8001 STRH r1,[r0,#0] ;1147
000020 bd30 POP {r4,r5,pc}
;;;1151
ENDP
000022 0000 DCW 0x0000
|L26.36|
DCD 0x40023c16
AREA ||i.FLASH_OB_PCROPSelectionConfig||, CODE, READONLY, ALIGN=2
FLASH_OB_PCROPSelectionConfig PROC
;;;1098 */
;;;1099 void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP)
000000 4a03 LDR r2,|L27.16|
;;;1100 {
;;;1101 uint8_t optiontmp = 0xFF;
;;;1102
;;;1103 /* Check the parameters */
;;;1104 assert_param(IS_OB_PCROP_SELECT(OB_PcROP));
;;;1105
;;;1106 /* Mask SPRMOD bit */
;;;1107 optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
000002 7811 LDRB r1,[r2,#0]
000004 f001017f AND r1,r1,#0x7f
;;;1108 /* Update Option Byte */
;;;1109 *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PcROP | optiontmp);
000008 4308 ORRS r0,r0,r1
00000a 7010 STRB r0,[r2,#0]
;;;1110
;;;1111 }
00000c 4770 BX lr
;;;1112
ENDP
00000e 0000 DCW 0x0000
|L27.16|
DCD 0x40023c17
AREA ||i.FLASH_OB_RDPConfig||, CODE, READONLY, ALIGN=2
FLASH_OB_RDPConfig PROC
;;;1201 */
;;;1202 void FLASH_OB_RDPConfig(uint8_t OB_RDP)
000000 b510 PUSH {r4,lr}
;;;1203 {
000002 4604 MOV r4,r0
;;;1204 FLASH_Status status = FLASH_COMPLETE;
;;;1205
;;;1206 /* Check the parameters */
;;;1207 assert_param(IS_OB_RDP(OB_RDP));
;;;1208
;;;1209 status = FLASH_WaitForLastOperation();
000004 f7fffffe BL FLASH_WaitForLastOperation
;;;1210
;;;1211 if(status == FLASH_COMPLETE)
000008 2809 CMP r0,#9
00000a d101 BNE |L28.16|
;;;1212 {
;;;1213 *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP;
00000c 4801 LDR r0,|L28.20|
00000e 7004 STRB r4,[r0,#0]
|L28.16|
;;;1214
;;;1215 }
;;;1216 }
000010 bd10 POP {r4,pc}
;;;1217
ENDP
000012 0000 DCW 0x0000
|L28.20|
DCD 0x40023c15
AREA ||i.FLASH_OB_Unlock||, CODE, READONLY, ALIGN=2
FLASH_OB_Unlock PROC
;;;968 */
;;;969 void FLASH_OB_Unlock(void)
000000 4805 LDR r0,|L29.24|
;;;970 {
;;;971 if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
000002 6800 LDR r0,[r0,#0]
000004 07c0 LSLS r0,r0,#31
000006 d005 BEQ |L29.20|
;;;972 {
;;;973 /* Authorizes the Option Byte register programming */
;;;974 FLASH->OPTKEYR = FLASH_OPT_KEY1;
000008 4803 LDR r0,|L29.24|
00000a 4904 LDR r1,|L29.28|
00000c 380c SUBS r0,r0,#0xc
00000e 6001 STR r1,[r0,#0]
;;;975 FLASH->OPTKEYR = FLASH_OPT_KEY2;
000010 4903 LDR r1,|L29.32|
000012 6001 STR r1,[r0,#0]
|L29.20|
;;;976 }
;;;977 }
000014 4770 BX lr
;;;978
ENDP
000016 0000 DCW 0x0000
|L29.24|
DCD 0x40023c14
|L29.28|
DCD 0x08192a3b
|L29.32|
DCD 0x4c5d6e7f
AREA ||i.FLASH_OB_UserConfig||, CODE, READONLY, ALIGN=2
FLASH_OB_UserConfig PROC
;;;1233 */
;;;1234 void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
000000 b570 PUSH {r4-r6,lr}
;;;1235 {
000002 4605 MOV r5,r0
000004 460c MOV r4,r1
000006 4616 MOV r6,r2
;;;1236 uint8_t optiontmp = 0xFF;
;;;1237 FLASH_Status status = FLASH_COMPLETE;
;;;1238
;;;1239 /* Check the parameters */
;;;1240 assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
;;;1241 assert_param(IS_OB_STOP_SOURCE(OB_STOP));
;;;1242 assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
;;;1243
;;;1244 /* Wait for last operation to be completed */
;;;1245 status = FLASH_WaitForLastOperation();
000008 f7fffffe BL FLASH_WaitForLastOperation
;;;1246
;;;1247 if(status == FLASH_COMPLETE)
00000c 2809 CMP r0,#9
00000e d107 BNE |L30.32|
;;;1248 {
;;;1249 #if defined(STM32F427_437xx) || defined(STM32F429_439xx)
;;;1250 /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
;;;1251 optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);
;;;1252 #endif /* STM32F427_437xx || STM32F429_439xx */
;;;1253
;;;1254 #if defined(STM32F40_41xxx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F446xx)
;;;1255 /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */
;;;1256 optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F);
000010 4a04 LDR r2,|L30.36|
000012 7810 LDRB r0,[r2,#0]
000014 f000000f AND r0,r0,#0xf
;;;1257 #endif /* STM32F40_41xxx || STM32F401xx || STM32F411xE || STM32F446xx */
;;;1258
;;;1259 /* Update User Option Byte */
;;;1260 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp)));
000018 4304 ORRS r4,r4,r0
00001a 4334 ORRS r4,r4,r6
00001c 432c ORRS r4,r4,r5
00001e 7014 STRB r4,[r2,#0]
|L30.32|
;;;1261 }
;;;1262 }
000020 bd70 POP {r4-r6,pc}
;;;1263
ENDP
000022 0000 DCW 0x0000
|L30.36|
DCD 0x40023c14
AREA ||i.FLASH_OB_WRP1Config||, CODE, READONLY, ALIGN=2
FLASH_OB_WRP1Config PROC
;;;1048 */
;;;1049 void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
000000 b530 PUSH {r4,r5,lr}
;;;1050 {
000002 4604 MOV r4,r0
000004 460d MOV r5,r1
;;;1051 FLASH_Status status = FLASH_COMPLETE;
;;;1052
;;;1053 /* Check the parameters */
;;;1054 assert_param(IS_OB_WRP(OB_WRP));
;;;1055 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1056
;;;1057 status = FLASH_WaitForLastOperation();
000006 f7fffffe BL FLASH_WaitForLastOperation
;;;1058
;;;1059 if(status == FLASH_COMPLETE)
00000a 2809 CMP r0,#9
00000c d104 BNE |L31.24|
;;;1060 {
;;;1061 if(NewState != DISABLE)
;;;1062 {
;;;1063 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_WRP);
00000e 4805 LDR r0,|L31.36|
000010 b11d CBZ r5,|L31.26|
000012 8801 LDRH r1,[r0,#0]
000014 43a1 BICS r1,r1,r4
000016 8001 STRH r1,[r0,#0]
|L31.24|
;;;1064 }
;;;1065 else
;;;1066 {
;;;1067 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
;;;1068 }
;;;1069 }
;;;1070 }
000018 bd30 POP {r4,r5,pc}
|L31.26|
00001a 8801 LDRH r1,[r0,#0] ;1067
00001c 4321 ORRS r1,r1,r4 ;1067
00001e 8001 STRH r1,[r0,#0] ;1067
000020 bd30 POP {r4,r5,pc}
;;;1071
ENDP
000022 0000 DCW 0x0000
|L31.36|
DCD 0x40023c1a
AREA ||i.FLASH_OB_WRPConfig||, CODE, READONLY, ALIGN=2
FLASH_OB_WRPConfig PROC
;;;1006 */
;;;1007 void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
000000 b530 PUSH {r4,r5,lr}
;;;1008 {
000002 4604 MOV r4,r0
000004 460d MOV r5,r1
;;;1009 FLASH_Status status = FLASH_COMPLETE;
;;;1010
;;;1011 /* Check the parameters */
;;;1012 assert_param(IS_OB_WRP(OB_WRP));
;;;1013 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1014
;;;1015 status = FLASH_WaitForLastOperation();
000006 f7fffffe BL FLASH_WaitForLastOperation
;;;1016
;;;1017 if(status == FLASH_COMPLETE)
00000a 2809 CMP r0,#9
00000c d104 BNE |L32.24|
;;;1018 {
;;;1019 if(NewState != DISABLE)
;;;1020 {
;;;1021 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP);
00000e 4805 LDR r0,|L32.36|
000010 b11d CBZ r5,|L32.26|
000012 8801 LDRH r1,[r0,#0]
000014 43a1 BICS r1,r1,r4
000016 8001 STRH r1,[r0,#0]
|L32.24|
;;;1022 }
;;;1023 else
;;;1024 {
;;;1025 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
;;;1026 }
;;;1027 }
;;;1028 }
000018 bd30 POP {r4,r5,pc}
|L32.26|
00001a 8801 LDRH r1,[r0,#0] ;1025
00001c 4321 ORRS r1,r1,r4 ;1025
00001e 8001 STRH r1,[r0,#0] ;1025
000020 bd30 POP {r4,r5,pc}
;;;1029
ENDP
000022 0000 DCW 0x0000
|L32.36|
DCD 0x40023c16
AREA ||i.FLASH_PrefetchBufferCmd||, CODE, READONLY, ALIGN=2
FLASH_PrefetchBufferCmd PROC
;;;292 */
;;;293 void FLASH_PrefetchBufferCmd(FunctionalState NewState)
000000 4906 LDR r1,|L33.28|
;;;294 {
;;;295 /* Check the parameters */
;;;296 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;297
;;;298 /* Enable or disable the Prefetch Buffer */
;;;299 if(NewState != DISABLE)
000002 2800 CMP r0,#0
000004 d004 BEQ |L33.16|
;;;300 {
;;;301 FLASH->ACR |= FLASH_ACR_PRFTEN;
000006 6808 LDR r0,[r1,#0]
000008 f4407080 ORR r0,r0,#0x100
00000c 6008 STR r0,[r1,#0]
;;;302 }
;;;303 else
;;;304 {
;;;305 FLASH->ACR &= (~FLASH_ACR_PRFTEN);
;;;306 }
;;;307 }
00000e 4770 BX lr
|L33.16|
000010 6808 LDR r0,[r1,#0] ;305
000012 f4207080 BIC r0,r0,#0x100 ;305
000016 6008 STR r0,[r1,#0] ;305
000018 4770 BX lr
;;;308
ENDP
00001a 0000 DCW 0x0000
|L33.28|
DCD 0x40023c00
AREA ||i.FLASH_ProgramByte||, CODE, READONLY, ALIGN=2
FLASH_ProgramByte PROC
;;;869 */
;;;870 FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
000000 b570 PUSH {r4-r6,lr}
;;;871 {
000002 4606 MOV r6,r0
000004 460d MOV r5,r1
;;;872 FLASH_Status status = FLASH_COMPLETE;
;;;873
;;;874 /* Check the parameters */
;;;875 assert_param(IS_FLASH_ADDRESS(Address));
;;;876
;;;877 /* Wait for last operation to be completed */
;;;878 status = FLASH_WaitForLastOperation();
000006 f7fffffe BL FLASH_WaitForLastOperation
;;;879
;;;880 if(status == FLASH_COMPLETE)
00000a 2809 CMP r0,#9
00000c d111 BNE |L34.50|
;;;881 {
;;;882 /* if the previous operation is completed, proceed to program the new data */
;;;883 FLASH->CR &= CR_PSIZE_MASK;
00000e 4c09 LDR r4,|L34.52|
000010 6820 LDR r0,[r4,#0]
000012 f4207040 BIC r0,r0,#0x300
000016 6020 STR r0,[r4,#0]
;;;884 FLASH->CR |= FLASH_PSIZE_BYTE;
000018 6820 LDR r0,[r4,#0]
00001a 6020 STR r0,[r4,#0]
;;;885 FLASH->CR |= FLASH_CR_PG;
00001c 6820 LDR r0,[r4,#0]
00001e f0400001 ORR r0,r0,#1
000022 6020 STR r0,[r4,#0]
;;;886
;;;887 *(__IO uint8_t*)Address = Data;
000024 7035 STRB r5,[r6,#0]
;;;888
;;;889 /* Wait for last operation to be completed */
;;;890 status = FLASH_WaitForLastOperation();
000026 f7fffffe BL FLASH_WaitForLastOperation
;;;891
;;;892 /* if the program operation is completed, disable the PG Bit */
;;;893 FLASH->CR &= (~FLASH_CR_PG);
00002a 6821 LDR r1,[r4,#0]
00002c f0210101 BIC r1,r1,#1
000030 6021 STR r1,[r4,#0]
|L34.50|
;;;894 }
;;;895
;;;896 /* Return the Program Status */
;;;897 return status;
;;;898 }
000032 bd70 POP {r4-r6,pc}
;;;899
ENDP
|L34.52|
DCD 0x40023c10
AREA ||i.FLASH_ProgramDoubleWord||, CODE, READONLY, ALIGN=2
FLASH_ProgramDoubleWord PROC
;;;742 */
;;;743 FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
000000 b5f0 PUSH {r4-r7,lr}
;;;744 {
000002 4607 MOV r7,r0
000004 4615 MOV r5,r2
000006 461e MOV r6,r3
;;;745 FLASH_Status status = FLASH_COMPLETE;
;;;746
;;;747 /* Check the parameters */
;;;748 assert_param(IS_FLASH_ADDRESS(Address));
;;;749
;;;750 /* Wait for last operation to be completed */
;;;751 status = FLASH_WaitForLastOperation();
000008 f7fffffe BL FLASH_WaitForLastOperation
;;;752
;;;753 if(status == FLASH_COMPLETE)
00000c 2809 CMP r0,#9
00000e d114 BNE |L35.58|
;;;754 {
;;;755 /* if the previous operation is completed, proceed to program the new data */
;;;756 FLASH->CR &= CR_PSIZE_MASK;
000010 4c0a LDR r4,|L35.60|
000012 6820 LDR r0,[r4,#0]
000014 f4207040 BIC r0,r0,#0x300
000018 6020 STR r0,[r4,#0]
;;;757 FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
00001a 6820 LDR r0,[r4,#0]
00001c f4407040 ORR r0,r0,#0x300
000020 6020 STR r0,[r4,#0]
;;;758 FLASH->CR |= FLASH_CR_PG;
000022 6820 LDR r0,[r4,#0]
000024 f0400001 ORR r0,r0,#1
000028 6020 STR r0,[r4,#0]
;;;759
;;;760 *(__IO uint64_t*)Address = Data;
00002a 603d STR r5,[r7,#0]
00002c 607e STR r6,[r7,#4]
;;;761
;;;762 /* Wait for last operation to be completed */
;;;763 status = FLASH_WaitForLastOperation();
00002e f7fffffe BL FLASH_WaitForLastOperation
;;;764
;;;765 /* if the program operation is completed, disable the PG Bit */
;;;766 FLASH->CR &= (~FLASH_CR_PG);
000032 6821 LDR r1,[r4,#0]
000034 f0210101 BIC r1,r1,#1
000038 6021 STR r1,[r4,#0]
|L35.58|
;;;767 }
;;;768 /* Return the Program Status */
;;;769 return status;
;;;770 }
00003a bdf0 POP {r4-r7,pc}
;;;771
ENDP
|L35.60|
DCD 0x40023c10
AREA ||i.FLASH_ProgramHalfWord||, CODE, READONLY, ALIGN=2
FLASH_ProgramHalfWord PROC
;;;827 */
;;;828 FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
000000 b570 PUSH {r4-r6,lr}
;;;829 {
000002 4605 MOV r5,r0
000004 460e MOV r6,r1
;;;830 FLASH_Status status = FLASH_COMPLETE;
;;;831
;;;832 /* Check the parameters */
;;;833 assert_param(IS_FLASH_ADDRESS(Address));
;;;834
;;;835 /* Wait for last operation to be completed */
;;;836 status = FLASH_WaitForLastOperation();
000006 f7fffffe BL FLASH_WaitForLastOperation
;;;837
;;;838 if(status == FLASH_COMPLETE)
00000a 2809 CMP r0,#9
00000c d113 BNE |L36.54|
;;;839 {
;;;840 /* if the previous operation is completed, proceed to program the new data */
;;;841 FLASH->CR &= CR_PSIZE_MASK;
00000e 4c0a LDR r4,|L36.56|
000010 6820 LDR r0,[r4,#0]
000012 f4207040 BIC r0,r0,#0x300
000016 6020 STR r0,[r4,#0]
;;;842 FLASH->CR |= FLASH_PSIZE_HALF_WORD;
000018 6820 LDR r0,[r4,#0]
00001a f4407080 ORR r0,r0,#0x100
00001e 6020 STR r0,[r4,#0]
;;;843 FLASH->CR |= FLASH_CR_PG;
000020 6820 LDR r0,[r4,#0]
000022 f0400001 ORR r0,r0,#1
000026 6020 STR r0,[r4,#0]
;;;844
;;;845 *(__IO uint16_t*)Address = Data;
000028 802e STRH r6,[r5,#0]
;;;846
;;;847 /* Wait for last operation to be completed */
;;;848 status = FLASH_WaitForLastOperation();
00002a f7fffffe BL FLASH_WaitForLastOperation
;;;849
;;;850 /* if the program operation is completed, disable the PG Bit */
;;;851 FLASH->CR &= (~FLASH_CR_PG);
00002e 6821 LDR r1,[r4,#0]
000030 f0210101 BIC r1,r1,#1
000034 6021 STR r1,[r4,#0]
|L36.54|
;;;852 }
;;;853 /* Return the Program Status */
;;;854 return status;
;;;855 }
000036 bd70 POP {r4-r6,pc}
;;;856
ENDP
|L36.56|
DCD 0x40023c10
AREA ||i.FLASH_ProgramWord||, CODE, READONLY, ALIGN=2
FLASH_ProgramWord PROC
;;;785 */
;;;786 FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
000000 b570 PUSH {r4-r6,lr}
;;;787 {
000002 4605 MOV r5,r0
000004 460e MOV r6,r1
;;;788 FLASH_Status status = FLASH_COMPLETE;
;;;789
;;;790 /* Check the parameters */
;;;791 assert_param(IS_FLASH_ADDRESS(Address));
;;;792
;;;793 /* Wait for last operation to be completed */
;;;794 status = FLASH_WaitForLastOperation();
000006 f7fffffe BL FLASH_WaitForLastOperation
;;;795
;;;796 if(status == FLASH_COMPLETE)
00000a 2809 CMP r0,#9
00000c d113 BNE |L37.54|
;;;797 {
;;;798 /* if the previous operation is completed, proceed to program the new data */
;;;799 FLASH->CR &= CR_PSIZE_MASK;
00000e 4c0a LDR r4,|L37.56|
000010 6820 LDR r0,[r4,#0]
000012 f4207040 BIC r0,r0,#0x300
000016 6020 STR r0,[r4,#0]
;;;800 FLASH->CR |= FLASH_PSIZE_WORD;
000018 6820 LDR r0,[r4,#0]
00001a f4407000 ORR r0,r0,#0x200
00001e 6020 STR r0,[r4,#0]
;;;801 FLASH->CR |= FLASH_CR_PG;
000020 6820 LDR r0,[r4,#0]
000022 f0400001 ORR r0,r0,#1
000026 6020 STR r0,[r4,#0]
;;;802
;;;803 *(__IO uint32_t*)Address = Data;
000028 602e STR r6,[r5,#0]
;;;804
;;;805 /* Wait for last operation to be completed */
;;;806 status = FLASH_WaitForLastOperation();
00002a f7fffffe BL FLASH_WaitForLastOperation
;;;807
;;;808 /* if the program operation is completed, disable the PG Bit */
;;;809 FLASH->CR &= (~FLASH_CR_PG);
00002e 6821 LDR r1,[r4,#0]
000030 f0210101 BIC r1,r1,#1
000034 6021 STR r1,[r4,#0]
|L37.54|
;;;810 }
;;;811 /* Return the Program Status */
;;;812 return status;
;;;813 }
000036 bd70 POP {r4-r6,pc}
;;;814
ENDP
|L37.56|
DCD 0x40023c10
AREA ||i.FLASH_SetLatency||, CODE, READONLY, ALIGN=2
FLASH_SetLatency PROC
;;;277 */
;;;278 void FLASH_SetLatency(uint32_t FLASH_Latency)
000000 4901 LDR r1,|L38.8|
;;;279 {
;;;280 /* Check the parameters */
;;;281 assert_param(IS_FLASH_LATENCY(FLASH_Latency));
;;;282
;;;283 /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */
;;;284 *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency;
000002 7008 STRB r0,[r1,#0]
;;;285 }
000004 4770 BX lr
;;;286
ENDP
000006 0000 DCW 0x0000
|L38.8|
DCD 0x40023c00
AREA ||i.FLASH_Unlock||, CODE, READONLY, ALIGN=2
FLASH_Unlock PROC
;;;414 */
;;;415 void FLASH_Unlock(void)
000000 4805 LDR r0,|L39.24|
;;;416 {
;;;417 if((FLASH->CR & FLASH_CR_LOCK) != RESET)
000002 6800 LDR r0,[r0,#0]
000004 2800 CMP r0,#0
000006 da05 BGE |L39.20|
;;;418 {
;;;419 /* Authorize the FLASH Registers access */
;;;420 FLASH->KEYR = FLASH_KEY1;
000008 4803 LDR r0,|L39.24|
00000a 4904 LDR r1,|L39.28|
00000c 380c SUBS r0,r0,#0xc
00000e 6001 STR r1,[r0,#0]
;;;421 FLASH->KEYR = FLASH_KEY2;
000010 4903 LDR r1,|L39.32|
000012 6001 STR r1,[r0,#0]
|L39.20|
;;;422 }
;;;423 }
000014 4770 BX lr
;;;424
ENDP
000016 0000 DCW 0x0000
|L39.24|
DCD 0x40023c10
|L39.28|
DCD 0x45670123
|L39.32|
DCD 0xcdef89ab
AREA ||i.FLASH_WaitForLastOperation||, CODE, READONLY, ALIGN=1
FLASH_WaitForLastOperation PROC
;;;1578 */
;;;1579 FLASH_Status FLASH_WaitForLastOperation(void)
000000 b508 PUSH {r3,lr}
;;;1580 {
;;;1581
;;;1582
;;;1583 __IO FLASH_Status status = FLASH_COMPLETE;
000002 2009 MOVS r0,#9
000004 9000 STR r0,[sp,#0]
;;;1584
;;;1585 /* Check for the FLASH Status */
;;;1586 status = FLASH_GetStatus();
000006 f7fffffe BL FLASH_GetStatus
00000a 9000 STR r0,[sp,#0]
;;;1587
;;;1588 /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
;;;1589 Even if the FLASH operation fails, the BUSY flag will be reset and an error
;;;1590 flag will be set */
;;;1591 while(status == FLASH_BUSY)
00000c e002 B |L40.20|
|L40.14|
;;;1592 {
;;;1593 status = FLASH_GetStatus();
00000e f7fffffe BL FLASH_GetStatus
000012 9000 STR r0,[sp,#0]
|L40.20|
000014 f89d0000 LDRB r0,[sp,#0] ;1591
000018 2801 CMP r0,#1 ;1591
00001a d0f8 BEQ |L40.14|
;;;1594
;;;1595 }
;;;1596 /* Return the operation status */
;;;1597 return status;
00001c f89d0000 LDRB r0,[sp,#0]
;;;1598 }
000020 bd08 POP {r3,pc}
;;;1599
ENDP
;*** Start embedded assembler ***
#line 1 "..\\..\\Libraries\\STM32F4xx_StdPeriph_Driver\\src\\stm32f4xx_flash.c"
AREA ||.rev16_text||, CODE
THUMB
EXPORT |__asm___17_stm32f4xx_flash_c_a2a150d6____REV16|
#line 129 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h"
|__asm___17_stm32f4xx_flash_c_a2a150d6____REV16| PROC
#line 130
rev16 r0, r0
bx lr
ENDP
AREA ||.revsh_text||, CODE
THUMB
EXPORT |__asm___17_stm32f4xx_flash_c_a2a150d6____REVSH|
#line 144
|__asm___17_stm32f4xx_flash_c_a2a150d6____REVSH| PROC
#line 145
revsh r0, r0
bx lr
ENDP
AREA ||.rrx_text||, CODE
THUMB
EXPORT |__asm___17_stm32f4xx_flash_c_a2a150d6____RRX|
#line 300
|__asm___17_stm32f4xx_flash_c_a2a150d6____RRX| PROC
#line 301
rrx r0, r0
bx lr
ENDP
;*** End embedded assembler ***