AGV / agv_gelinmei · Files

stm32f4xx_dma.txt 50.1 KB
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; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\flash\obj\stm32f4xx_dma.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\stm32f4xx_dma.d --cpu=Cortex-M4.fp --apcs=interwork -O1 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Include -I..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\uCOS-III\uC-CPU -I..\..\uCOS-III\uC-LIB -I..\..\uCOS-III\uCOS-III\Ports -I..\..\uCOS-III\uCOS-III\Source -I..\..\uCOS-III\uC-CPU\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uC-LIB\Ports\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uCOS-III\Ports\ARM-Cortex-M4\Generic\RealView -I..\..\User -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\libapp -I..\..\RL-ARM\Config -I..\..\RL-ARM\Driver -I..\..\RL-ARM\RL-RTX\inc -I..\..\User\bsp\BSP -I..\..\RL-ARM\RL-CAN -I..\..\Libraries\DSP_LIB\Include -I..\..\MODBUS\modbus\rtu -I..\..\MODBUS\BARE\port -I..\..\MODBUS\modbus\include -I..\..\User\bsp\BSP -I..\..\PLC -I..\..\Avoid -I..\..\User\parameter -I..\..\User\LaserMotionCtr -I..\..\User\W5100S -I..\..\User\bsp -I..\..\User\CHASSIS -I..\..\User\CONTROLFUNCTION -I..\..\User\DATAUPDATE -I..\..\User\HARAWARE -I..\..\User\MOTORDRIVER -I..\..\User\NAVAGATION -I..\..\User\PLATFORM -I..\..\User\SENSOR -I.\RTE\_Flash -IC:\Users\YDJ\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include -IC:\Users\YDJ\AppData\Local\Arm\Packs\Keil\STM32F4xx_DFP\2.13.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include -D__UVISION_VERSION=527 -D_RTE_ -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -D__RTX -D__FPU_USED=1 --omf_browse=.\flash\obj\stm32f4xx_dma.crf ..\..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dma.c]
                          THUMB

                          AREA ||i.DMA_ClearFlag||, CODE, READONLY, ALIGN=2

                  DMA_ClearFlag PROC
;;;1070     */
;;;1071   void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
000000  4a07              LDR      r2,|L1.32|
;;;1072   {
;;;1073     DMA_TypeDef* DMAy;
;;;1074   
;;;1075     /* Check the parameters */
;;;1076     assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;1077     assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
;;;1078   
;;;1079     /* Determine the DMA to which belongs the stream */
;;;1080     if (DMAy_Streamx < DMA2_Stream0)
000002  4290              CMP      r0,r2
000004  d201              BCS      |L1.10|
;;;1081     {
;;;1082       /* DMAy_Streamx belongs to DMA1 */
;;;1083       DMAy = DMA1; 
000006  4807              LDR      r0,|L1.36|
000008  e001              B        |L1.14|
                  |L1.10|
;;;1084     } 
;;;1085     else 
;;;1086     {
;;;1087       /* DMAy_Streamx belongs to DMA2 */
;;;1088       DMAy = DMA2; 
00000a  4805              LDR      r0,|L1.32|
00000c  3810              SUBS     r0,r0,#0x10
                  |L1.14|
;;;1089     }
;;;1090   
;;;1091     /* Check if LIFCR or HIFCR register is targeted */
;;;1092     if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
;;;1093     {
;;;1094       /* Set DMAy HIFCR register clear flag bits */
;;;1095       DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
00000e  4a06              LDR      r2,|L1.40|
000010  008b              LSLS     r3,r1,#2              ;1092
000012  ea010102          AND      r1,r1,r2
000016  d501              BPL      |L1.28|
000018  60c1              STR      r1,[r0,#0xc]
;;;1096     }
;;;1097     else 
;;;1098     {
;;;1099       /* Set DMAy LIFCR register clear flag bits */
;;;1100       DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
;;;1101     }    
;;;1102   }
00001a  4770              BX       lr
                  |L1.28|
00001c  6081              STR      r1,[r0,#8]            ;1100
00001e  4770              BX       lr
;;;1103   
                          ENDP

                  |L1.32|
                          DCD      0x40026410
                  |L1.36|
                          DCD      0x40026000
                  |L1.40|
                          DCD      0x0f7d0f7d

                          AREA ||i.DMA_ClearITPendingBit||, CODE, READONLY, ALIGN=2

                  DMA_ClearITPendingBit PROC
;;;1251     */
;;;1252   void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
000000  4a07              LDR      r2,|L2.32|
;;;1253   {
;;;1254     DMA_TypeDef* DMAy;
;;;1255   
;;;1256     /* Check the parameters */
;;;1257     assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;1258     assert_param(IS_DMA_CLEAR_IT(DMA_IT));
;;;1259   
;;;1260     /* Determine the DMA to which belongs the stream */
;;;1261     if (DMAy_Streamx < DMA2_Stream0)
000002  4290              CMP      r0,r2
000004  d201              BCS      |L2.10|
;;;1262     {
;;;1263       /* DMAy_Streamx belongs to DMA1 */
;;;1264       DMAy = DMA1; 
000006  4807              LDR      r0,|L2.36|
000008  e001              B        |L2.14|
                  |L2.10|
;;;1265     } 
;;;1266     else 
;;;1267     {
;;;1268       /* DMAy_Streamx belongs to DMA2 */
;;;1269       DMAy = DMA2; 
00000a  4805              LDR      r0,|L2.32|
00000c  3810              SUBS     r0,r0,#0x10
                  |L2.14|
;;;1270     }
;;;1271   
;;;1272     /* Check if LIFCR or HIFCR register is targeted */
;;;1273     if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
;;;1274     {
;;;1275       /* Set DMAy HIFCR register clear interrupt bits */
;;;1276       DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
00000e  4a06              LDR      r2,|L2.40|
000010  008b              LSLS     r3,r1,#2              ;1273
000012  ea010102          AND      r1,r1,r2
000016  d501              BPL      |L2.28|
000018  60c1              STR      r1,[r0,#0xc]
;;;1277     }
;;;1278     else 
;;;1279     {
;;;1280       /* Set DMAy LIFCR register clear interrupt bits */
;;;1281       DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
;;;1282     }   
;;;1283   }
00001a  4770              BX       lr
                  |L2.28|
00001c  6081              STR      r1,[r0,#8]            ;1281
00001e  4770              BX       lr
;;;1284   
                          ENDP

                  |L2.32|
                          DCD      0x40026410
                  |L2.36|
                          DCD      0x40026000
                  |L2.40|
                          DCD      0x0f7d0f7d

                          AREA ||i.DMA_Cmd||, CODE, READONLY, ALIGN=1

                  DMA_Cmd PROC
;;;477      */
;;;478    void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;479    {
000002  d004              BEQ      |L3.14|
;;;480      /* Check the parameters */
;;;481      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;482      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;483    
;;;484      if (NewState != DISABLE)
;;;485      {
;;;486        /* Enable the selected DMAy Streamx by setting EN bit */
;;;487        DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN;
000004  6801              LDR      r1,[r0,#0]
000006  f0410101          ORR      r1,r1,#1
00000a  6001              STR      r1,[r0,#0]
;;;488      }
;;;489      else
;;;490      {
;;;491        /* Disable the selected DMAy Streamx by clearing EN bit */
;;;492        DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN;
;;;493      }
;;;494    }
00000c  4770              BX       lr
                  |L3.14|
00000e  6801              LDR      r1,[r0,#0]            ;492
000010  f0210101          BIC      r1,r1,#1              ;492
000014  6001              STR      r1,[r0,#0]            ;492
000016  4770              BX       lr
;;;495    
                          ENDP


                          AREA ||i.DMA_DeInit||, CODE, READONLY, ALIGN=2

                  DMA_DeInit PROC
;;;195      */
;;;196    void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx)
000000  e92d43f0          PUSH     {r4-r9,lr}
;;;197    {
;;;198      /* Check the parameters */
;;;199      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;200    
;;;201      /* Disable the selected DMAy Streamx */
;;;202      DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN);
000004  6801              LDR      r1,[r0,#0]
000006  f0210101          BIC      r1,r1,#1
00000a  6001              STR      r1,[r0,#0]
;;;203    
;;;204      /* Reset DMAy Streamx control register */
;;;205      DMAy_Streamx->CR  = 0;
00000c  2100              MOVS     r1,#0
00000e  6001              STR      r1,[r0,#0]
;;;206      
;;;207      /* Reset DMAy Streamx Number of Data to Transfer register */
;;;208      DMAy_Streamx->NDTR = 0;
000010  6041              STR      r1,[r0,#4]
;;;209      
;;;210      /* Reset DMAy Streamx peripheral address register */
;;;211      DMAy_Streamx->PAR  = 0;
000012  6081              STR      r1,[r0,#8]
;;;212      
;;;213      /* Reset DMAy Streamx memory 0 address register */
;;;214      DMAy_Streamx->M0AR = 0;
000014  60c1              STR      r1,[r0,#0xc]
;;;215    
;;;216      /* Reset DMAy Streamx memory 1 address register */
;;;217      DMAy_Streamx->M1AR = 0;
000016  6101              STR      r1,[r0,#0x10]
;;;218    
;;;219      /* Reset DMAy Streamx FIFO control register */
;;;220      DMAy_Streamx->FCR = (uint32_t)0x00000021; 
000018  2121              MOVS     r1,#0x21
00001a  6141              STR      r1,[r0,#0x14]
;;;221    
;;;222      /* Reset interrupt pending bits for the selected stream */
;;;223      if (DMAy_Streamx == DMA1_Stream0)
;;;224      {
;;;225        /* Reset interrupt pending bits for DMA1 Stream0 */
;;;226        DMA1->LIFCR = DMA_Stream0_IT_MASK;
00001c  493e              LDR      r1,|L4.280|
00001e  4a3e              LDR      r2,|L4.280|
000020  3910              SUBS     r1,r1,#0x10
000022  f04f083d          MOV      r8,#0x3d
000026  4290              CMP      r0,r2                 ;223
000028  d103              BNE      |L4.50|
00002a  f8c18008          STR      r8,[r1,#8]
                  |L4.46|
;;;227      }
;;;228      else if (DMAy_Streamx == DMA1_Stream1)
;;;229      {
;;;230        /* Reset interrupt pending bits for DMA1 Stream1 */
;;;231        DMA1->LIFCR = DMA_Stream1_IT_MASK;
;;;232      }
;;;233      else if (DMAy_Streamx == DMA1_Stream2)
;;;234      {
;;;235        /* Reset interrupt pending bits for DMA1 Stream2 */
;;;236        DMA1->LIFCR = DMA_Stream2_IT_MASK;
;;;237      }
;;;238      else if (DMAy_Streamx == DMA1_Stream3)
;;;239      {
;;;240        /* Reset interrupt pending bits for DMA1 Stream3 */
;;;241        DMA1->LIFCR = DMA_Stream3_IT_MASK;
;;;242      }
;;;243      else if (DMAy_Streamx == DMA1_Stream4)
;;;244      {
;;;245        /* Reset interrupt pending bits for DMA1 Stream4 */
;;;246        DMA1->HIFCR = DMA_Stream4_IT_MASK;
;;;247      }
;;;248      else if (DMAy_Streamx == DMA1_Stream5)
;;;249      {
;;;250        /* Reset interrupt pending bits for DMA1 Stream5 */
;;;251        DMA1->HIFCR = DMA_Stream5_IT_MASK;
;;;252      }
;;;253      else if (DMAy_Streamx == DMA1_Stream6)
;;;254      {
;;;255        /* Reset interrupt pending bits for DMA1 Stream6 */
;;;256        DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK;
;;;257      }
;;;258      else if (DMAy_Streamx == DMA1_Stream7)
;;;259      {
;;;260        /* Reset interrupt pending bits for DMA1 Stream7 */
;;;261        DMA1->HIFCR = DMA_Stream7_IT_MASK;
;;;262      }
;;;263      else if (DMAy_Streamx == DMA2_Stream0)
;;;264      {
;;;265        /* Reset interrupt pending bits for DMA2 Stream0 */
;;;266        DMA2->LIFCR = DMA_Stream0_IT_MASK;
;;;267      }
;;;268      else if (DMAy_Streamx == DMA2_Stream1)
;;;269      {
;;;270        /* Reset interrupt pending bits for DMA2 Stream1 */
;;;271        DMA2->LIFCR = DMA_Stream1_IT_MASK;
;;;272      }
;;;273      else if (DMAy_Streamx == DMA2_Stream2)
;;;274      {
;;;275        /* Reset interrupt pending bits for DMA2 Stream2 */
;;;276        DMA2->LIFCR = DMA_Stream2_IT_MASK;
;;;277      }
;;;278      else if (DMAy_Streamx == DMA2_Stream3)
;;;279      {
;;;280        /* Reset interrupt pending bits for DMA2 Stream3 */
;;;281        DMA2->LIFCR = DMA_Stream3_IT_MASK;
;;;282      }
;;;283      else if (DMAy_Streamx == DMA2_Stream4)
;;;284      {
;;;285        /* Reset interrupt pending bits for DMA2 Stream4 */
;;;286        DMA2->HIFCR = DMA_Stream4_IT_MASK;
;;;287      }
;;;288      else if (DMAy_Streamx == DMA2_Stream5)
;;;289      {
;;;290        /* Reset interrupt pending bits for DMA2 Stream5 */
;;;291        DMA2->HIFCR = DMA_Stream5_IT_MASK;
;;;292      }
;;;293      else if (DMAy_Streamx == DMA2_Stream6)
;;;294      {
;;;295        /* Reset interrupt pending bits for DMA2 Stream6 */
;;;296        DMA2->HIFCR = DMA_Stream6_IT_MASK;
;;;297      }
;;;298      else 
;;;299      {
;;;300        if (DMAy_Streamx == DMA2_Stream7)
;;;301        {
;;;302          /* Reset interrupt pending bits for DMA2 Stream7 */
;;;303          DMA2->HIFCR = DMA_Stream7_IT_MASK;
;;;304        }
;;;305      }
;;;306    }
00002e  e8bd83f0          POP      {r4-r9,pc}
                  |L4.50|
000032  4a39              LDR      r2,|L4.280|
000034  f44f6574          MOV      r5,#0xf40             ;231
000038  3218              ADDS     r2,r2,#0x18           ;228
00003a  4290              CMP      r0,r2                 ;228
00003c  d101              BNE      |L4.66|
00003e  608d              STR      r5,[r1,#8]            ;231
000040  e7f5              B        |L4.46|
                  |L4.66|
000042  4a35              LDR      r2,|L4.280|
000044  f44f1674          MOV      r6,#0x3d0000          ;236
000048  3230              ADDS     r2,r2,#0x30           ;233
00004a  4290              CMP      r0,r2                 ;233
00004c  d101              BNE      |L4.82|
00004e  608e              STR      r6,[r1,#8]            ;236
000050  e7ed              B        |L4.46|
                  |L4.82|
000052  4a31              LDR      r2,|L4.280|
000054  f04f6774          MOV      r7,#0xf400000         ;241
000058  3248              ADDS     r2,r2,#0x48           ;238
00005a  4290              CMP      r0,r2                 ;238
00005c  d101              BNE      |L4.98|
00005e  608f              STR      r7,[r1,#8]            ;241
000060  e7e5              B        |L4.46|
                  |L4.98|
000062  4b2d              LDR      r3,|L4.280|
000064  4a2d              LDR      r2,|L4.284|
000066  3360              ADDS     r3,r3,#0x60           ;243
000068  4298              CMP      r0,r3                 ;243
00006a  d101              BNE      |L4.112|
00006c  60ca              STR      r2,[r1,#0xc]          ;246
00006e  e7de              B        |L4.46|
                  |L4.112|
000070  4c29              LDR      r4,|L4.280|
000072  4b2b              LDR      r3,|L4.288|
000074  3478              ADDS     r4,r4,#0x78           ;248
000076  42a0              CMP      r0,r4                 ;248
000078  d101              BNE      |L4.126|
00007a  60cb              STR      r3,[r1,#0xc]          ;251
00007c  e7d7              B        |L4.46|
                  |L4.126|
00007e  f8dfc098          LDR      r12,|L4.280|
000082  4c28              LDR      r4,|L4.292|
000084  f10c0c90          ADD      r12,r12,#0x90         ;253
000088  4560              CMP      r0,r12                ;253
00008a  d101              BNE      |L4.144|
00008c  60cc              STR      r4,[r1,#0xc]          ;256
00008e  e7ce              B        |L4.46|
                  |L4.144|
000090  f8df9084          LDR      r9,|L4.280|
000094  f04f5c3d          MOV      r12,#0x2f400000       ;261
000098  f10909a8          ADD      r9,r9,#0xa8           ;258
00009c  4548              CMP      r0,r9                 ;258
00009e  d102              BNE      |L4.166|
0000a0  f8c1c00c          STR      r12,[r1,#0xc]         ;261
0000a4  e7c3              B        |L4.46|
                  |L4.166|
0000a6  4920              LDR      r1,|L4.296|
0000a8  f8df907c          LDR      r9,|L4.296|
0000ac  3908              SUBS     r1,r1,#8              ;266
0000ae  4548              CMP      r0,r9                 ;263
0000b0  d102              BNE      |L4.184|
0000b2  f8c18000          STR      r8,[r1,#0]            ;266
0000b6  e7ba              B        |L4.46|
                  |L4.184|
0000b8  f8df806c          LDR      r8,|L4.296|
0000bc  f1080818          ADD      r8,r8,#0x18           ;268
0000c0  4540              CMP      r0,r8                 ;268
0000c2  d101              BNE      |L4.200|
0000c4  600d              STR      r5,[r1,#0]            ;271
0000c6  e7b2              B        |L4.46|
                  |L4.200|
0000c8  4d17              LDR      r5,|L4.296|
0000ca  3530              ADDS     r5,r5,#0x30           ;273
0000cc  42a8              CMP      r0,r5                 ;273
0000ce  d101              BNE      |L4.212|
0000d0  600e              STR      r6,[r1,#0]            ;276
0000d2  e7ac              B        |L4.46|
                  |L4.212|
0000d4  4d14              LDR      r5,|L4.296|
0000d6  3548              ADDS     r5,r5,#0x48           ;278
0000d8  42a8              CMP      r0,r5                 ;278
0000da  d101              BNE      |L4.224|
0000dc  600f              STR      r7,[r1,#0]            ;281
0000de  e7a6              B        |L4.46|
                  |L4.224|
0000e0  4d11              LDR      r5,|L4.296|
0000e2  4911              LDR      r1,|L4.296|
0000e4  3560              ADDS     r5,r5,#0x60           ;283
0000e6  1f09              SUBS     r1,r1,#4              ;286
0000e8  42a8              CMP      r0,r5                 ;283
0000ea  d101              BNE      |L4.240|
0000ec  600a              STR      r2,[r1,#0]            ;286
0000ee  e79e              B        |L4.46|
                  |L4.240|
0000f0  4a0d              LDR      r2,|L4.296|
0000f2  3278              ADDS     r2,r2,#0x78           ;288
0000f4  4290              CMP      r0,r2                 ;288
0000f6  d101              BNE      |L4.252|
0000f8  600b              STR      r3,[r1,#0]            ;291
0000fa  e798              B        |L4.46|
                  |L4.252|
0000fc  4a0a              LDR      r2,|L4.296|
0000fe  3290              ADDS     r2,r2,#0x90           ;293
000100  4290              CMP      r0,r2                 ;293
000102  d101              BNE      |L4.264|
000104  600c              STR      r4,[r1,#0]            ;296
000106  e792              B        |L4.46|
                  |L4.264|
000108  4a07              LDR      r2,|L4.296|
00010a  32a8              ADDS     r2,r2,#0xa8           ;300
00010c  4290              CMP      r0,r2                 ;300
00010e  d18e              BNE      |L4.46|
000110  f8c1c000          STR      r12,[r1,#0]           ;303
000114  e78b              B        |L4.46|
;;;307    
                          ENDP

000116  0000              DCW      0x0000
                  |L4.280|
                          DCD      0x40026010
                  |L4.284|
                          DCD      0x2000003d
                  |L4.288|
                          DCD      0x20000f40
                  |L4.292|
                          DCD      0x203d0000
                  |L4.296|
                          DCD      0x40026410

                          AREA ||i.DMA_DoubleBufferModeCmd||, CODE, READONLY, ALIGN=1

                  DMA_DoubleBufferModeCmd PROC
;;;760      */
;;;761    void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;762    {  
000002  d004              BEQ      |L5.14|
;;;763      /* Check the parameters */
;;;764      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;765      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;766    
;;;767      /* Configure the Double Buffer mode */
;;;768      if (NewState != DISABLE)
;;;769      {
;;;770        /* Enable the Double buffer mode */
;;;771        DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM;
000004  6801              LDR      r1,[r0,#0]
000006  f4412180          ORR      r1,r1,#0x40000
00000a  6001              STR      r1,[r0,#0]
;;;772      }
;;;773      else
;;;774      {
;;;775        /* Disable the Double buffer mode */
;;;776        DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM;
;;;777      }
;;;778    }
00000c  4770              BX       lr
                  |L5.14|
00000e  6801              LDR      r1,[r0,#0]            ;776
000010  f4212180          BIC      r1,r1,#0x40000        ;776
000014  6001              STR      r1,[r0,#0]            ;776
000016  4770              BX       lr
;;;779    
                          ENDP


                          AREA ||i.DMA_DoubleBufferModeConfig||, CODE, READONLY, ALIGN=1

                  DMA_DoubleBufferModeConfig PROC
;;;729      */
;;;730    void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
000000  2a00              CMP      r2,#0
;;;731                                    uint32_t DMA_CurrentMemory)
;;;732    {  
000002  d004              BEQ      |L6.14|
;;;733      /* Check the parameters */
;;;734      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;735      assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory));
;;;736    
;;;737      if (DMA_CurrentMemory != DMA_Memory_0)
;;;738      {
;;;739        /* Set Memory 1 as current memory address */
;;;740        DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT);    
000004  6802              LDR      r2,[r0,#0]
000006  f4422200          ORR      r2,r2,#0x80000
00000a  6002              STR      r2,[r0,#0]
00000c  e003              B        |L6.22|
                  |L6.14|
;;;741      }
;;;742      else
;;;743      {
;;;744        /* Set Memory 0 as current memory address */
;;;745        DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT);    
00000e  6802              LDR      r2,[r0,#0]
000010  f4222200          BIC      r2,r2,#0x80000
000014  6002              STR      r2,[r0,#0]
                  |L6.22|
;;;746      }
;;;747    
;;;748      /* Write to DMAy Streamx M1AR */
;;;749      DMAy_Streamx->M1AR = Memory1BaseAddr;
000016  6101              STR      r1,[r0,#0x10]
;;;750    }
000018  4770              BX       lr
;;;751    
                          ENDP


                          AREA ||i.DMA_FlowControllerConfig||, CODE, READONLY, ALIGN=1

                  DMA_FlowControllerConfig PROC
;;;549      */
;;;550    void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl)
000000  2900              CMP      r1,#0
;;;551    {
000002  d004              BEQ      |L7.14|
;;;552      /* Check the parameters */
;;;553      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;554      assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl));
;;;555    
;;;556      /* Check the needed flow controller  */
;;;557      if(DMA_FlowCtrl != DMA_FlowCtrl_Memory)
;;;558      {
;;;559        /* Configure DMA_SxCR_PFCTRL bit with the input parameter */
;;;560        DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL;   
000004  6801              LDR      r1,[r0,#0]
000006  f0410120          ORR      r1,r1,#0x20
00000a  6001              STR      r1,[r0,#0]
;;;561      }
;;;562      else
;;;563      {
;;;564        /* Clear the PFCTRL bit: Memory is the flow controller */
;;;565        DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL;    
;;;566      }
;;;567    }
00000c  4770              BX       lr
                  |L7.14|
00000e  6801              LDR      r1,[r0,#0]            ;565
000010  f0210120          BIC      r1,r1,#0x20           ;565
000014  6001              STR      r1,[r0,#0]            ;565
000016  4770              BX       lr
;;;568    /**
                          ENDP


                          AREA ||i.DMA_GetCmdStatus||, CODE, READONLY, ALIGN=1

                  DMA_GetCmdStatus PROC
;;;942      */
;;;943    FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx)
000000  4601              MOV      r1,r0
;;;944    {
;;;945      FunctionalState state = DISABLE;
000002  2000              MOVS     r0,#0
;;;946    
;;;947      /* Check the parameters */
;;;948      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;949    
;;;950      if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0)
000004  6809              LDR      r1,[r1,#0]
000006  07c9              LSLS     r1,r1,#31
000008  d000              BEQ      |L8.12|
;;;951      {
;;;952        /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */
;;;953        state = ENABLE;
00000a  2001              MOVS     r0,#1
                  |L8.12|
;;;954      }
;;;955      else
;;;956      {
;;;957        /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and 
;;;958            all transfers are complete) */
;;;959        state = DISABLE;
;;;960      }
;;;961      return state;
;;;962    }
00000c  4770              BX       lr
;;;963    
                          ENDP


                          AREA ||i.DMA_GetCurrDataCounter||, CODE, READONLY, ALIGN=1

                  DMA_GetCurrDataCounter PROC
;;;646      */
;;;647    uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx)
000000  6840              LDR      r0,[r0,#4]
;;;648    {
;;;649      /* Check the parameters */
;;;650      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;651    
;;;652      /* Return the number of remaining data units for DMAy Streamx */
;;;653      return ((uint16_t)(DMAy_Streamx->NDTR));
000002  b280              UXTH     r0,r0
;;;654    }
000004  4770              BX       lr
;;;655    /**
                          ENDP


                          AREA ||i.DMA_GetCurrentMemoryTarget||, CODE, READONLY, ALIGN=1

                  DMA_GetCurrentMemoryTarget PROC
;;;827      */
;;;828    uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx)
000000  4601              MOV      r1,r0
;;;829    {
;;;830      uint32_t tmp = 0;
000002  2000              MOVS     r0,#0
;;;831      
;;;832      /* Check the parameters */
;;;833      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;834    
;;;835      /* Get the current memory target */
;;;836      if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0)
000004  6809              LDR      r1,[r1,#0]
000006  0309              LSLS     r1,r1,#12
000008  d500              BPL      |L10.12|
;;;837      {
;;;838        /* Current memory buffer used is Memory 1 */
;;;839        tmp = 1;
00000a  2001              MOVS     r0,#1
                  |L10.12|
;;;840      }  
;;;841      else
;;;842      {
;;;843        /* Current memory buffer used is Memory 0 */
;;;844        tmp = 0;    
;;;845      }
;;;846      return tmp;
;;;847    }
00000c  4770              BX       lr
;;;848    /**
                          ENDP


                          AREA ||i.DMA_GetFIFOStatus||, CODE, READONLY, ALIGN=1

                  DMA_GetFIFOStatus PROC
;;;976      */
;;;977    uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx)
000000  6940              LDR      r0,[r0,#0x14]
;;;978    {
;;;979      uint32_t tmpreg = 0;
;;;980     
;;;981      /* Check the parameters */
;;;982      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;983      
;;;984      /* Get the FIFO level bits */
;;;985      tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS));
000002  f0000038          AND      r0,r0,#0x38
;;;986      
;;;987      return tmpreg;
;;;988    }
000006  4770              BX       lr
;;;989    
                          ENDP


                          AREA ||i.DMA_GetFlagStatus||, CODE, READONLY, ALIGN=2

                  DMA_GetFlagStatus PROC
;;;1003     */
;;;1004   FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
000000  4602              MOV      r2,r0
;;;1005   {
;;;1006     FlagStatus bitstatus = RESET;
000002  2000              MOVS     r0,#0
;;;1007     DMA_TypeDef* DMAy;
;;;1008     uint32_t tmpreg = 0;
;;;1009   
;;;1010     /* Check the parameters */
;;;1011     assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;1012     assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
;;;1013   
;;;1014     /* Determine the DMA to which belongs the stream */
;;;1015     if (DMAy_Streamx < DMA2_Stream0)
000004  4b08              LDR      r3,|L12.40|
000006  429a              CMP      r2,r3
000008  d201              BCS      |L12.14|
;;;1016     {
;;;1017       /* DMAy_Streamx belongs to DMA1 */
;;;1018       DMAy = DMA1; 
00000a  4a08              LDR      r2,|L12.44|
00000c  e001              B        |L12.18|
                  |L12.14|
;;;1019     } 
;;;1020     else 
;;;1021     {
;;;1022       /* DMAy_Streamx belongs to DMA2 */
;;;1023       DMAy = DMA2; 
00000e  4a06              LDR      r2,|L12.40|
000010  3a10              SUBS     r2,r2,#0x10
                  |L12.18|
;;;1024     }
;;;1025   
;;;1026     /* Check if the flag is in HISR or LISR */
;;;1027     if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
000012  008b              LSLS     r3,r1,#2
000014  d501              BPL      |L12.26|
;;;1028     {
;;;1029       /* Get DMAy HISR register value */
;;;1030       tmpreg = DMAy->HISR;
000016  6852              LDR      r2,[r2,#4]
000018  e000              B        |L12.28|
                  |L12.26|
;;;1031     }
;;;1032     else
;;;1033     {
;;;1034       /* Get DMAy LISR register value */
;;;1035       tmpreg = DMAy->LISR;
00001a  6812              LDR      r2,[r2,#0]
                  |L12.28|
;;;1036     }   
;;;1037    
;;;1038     /* Mask the reserved bits */
;;;1039     tmpreg &= (uint32_t)RESERVED_MASK;
00001c  4b04              LDR      r3,|L12.48|
00001e  401a              ANDS     r2,r2,r3
;;;1040   
;;;1041     /* Check the status of the specified DMA flag */
;;;1042     if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
000020  420a              TST      r2,r1
000022  d000              BEQ      |L12.38|
;;;1043     {
;;;1044       /* DMA_FLAG is set */
;;;1045       bitstatus = SET;
000024  2001              MOVS     r0,#1
                  |L12.38|
;;;1046     }
;;;1047     else
;;;1048     {
;;;1049       /* DMA_FLAG is reset */
;;;1050       bitstatus = RESET;
;;;1051     }
;;;1052   
;;;1053     /* Return the DMA_FLAG status */
;;;1054     return  bitstatus;
;;;1055   }
000026  4770              BX       lr
;;;1056   
                          ENDP

                  |L12.40|
                          DCD      0x40026410
                  |L12.44|
                          DCD      0x40026000
                  |L12.48|
                          DCD      0x0f7d0f7d

                          AREA ||i.DMA_GetITStatus||, CODE, READONLY, ALIGN=2

                  DMA_GetITStatus PROC
;;;1169     */
;;;1170   ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
000000  b530              PUSH     {r4,r5,lr}
;;;1171   {
;;;1172     ITStatus bitstatus = RESET;
000002  2400              MOVS     r4,#0
;;;1173     DMA_TypeDef* DMAy;
;;;1174     uint32_t tmpreg = 0, enablestatus = 0;
;;;1175   
;;;1176     /* Check the parameters */
;;;1177     assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;1178     assert_param(IS_DMA_GET_IT(DMA_IT));
;;;1179    
;;;1180     /* Determine the DMA to which belongs the stream */
;;;1181     if (DMAy_Streamx < DMA2_Stream0)
000004  4a0f              LDR      r2,|L13.68|
000006  4290              CMP      r0,r2
000008  d201              BCS      |L13.14|
;;;1182     {
;;;1183       /* DMAy_Streamx belongs to DMA1 */
;;;1184       DMAy = DMA1; 
00000a  4a0f              LDR      r2,|L13.72|
00000c  e001              B        |L13.18|
                  |L13.14|
;;;1185     } 
;;;1186     else 
;;;1187     {
;;;1188       /* DMAy_Streamx belongs to DMA2 */
;;;1189       DMAy = DMA2; 
00000e  4a0d              LDR      r2,|L13.68|
000010  3a10              SUBS     r2,r2,#0x10
                  |L13.18|
;;;1190     }
;;;1191   
;;;1192     /* Check if the interrupt enable bit is in the CR or FCR register */
;;;1193     if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET)
000012  4b0e              LDR      r3,|L13.76|
000014  4219              TST      r1,r3
000016  d005              BEQ      |L13.36|
;;;1194     {
;;;1195       /* Get the interrupt enable position mask in CR register */
;;;1196       tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK);   
000018  231e              MOVS     r3,#0x1e
00001a  ea0325d1          AND      r5,r3,r1,LSR #11
;;;1197       
;;;1198       /* Check the enable bit in CR register */
;;;1199       enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg);
00001e  6803              LDR      r3,[r0,#0]
000020  402b              ANDS     r3,r3,r5
000022  e002              B        |L13.42|
                  |L13.36|
;;;1200     }
;;;1201     else 
;;;1202     {
;;;1203       /* Check the enable bit in FCR register */
;;;1204       enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE); 
000024  6940              LDR      r0,[r0,#0x14]
000026  f0000380          AND      r3,r0,#0x80
                  |L13.42|
;;;1205     }
;;;1206    
;;;1207     /* Check if the interrupt pending flag is in LISR or HISR */
;;;1208     if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
00002a  0088              LSLS     r0,r1,#2
00002c  d501              BPL      |L13.50|
;;;1209     {
;;;1210       /* Get DMAy HISR register value */
;;;1211       tmpreg = DMAy->HISR ;
00002e  6850              LDR      r0,[r2,#4]
000030  e000              B        |L13.52|
                  |L13.50|
;;;1212     }
;;;1213     else
;;;1214     {
;;;1215       /* Get DMAy LISR register value */
;;;1216       tmpreg = DMAy->LISR ;
000032  6810              LDR      r0,[r2,#0]
                  |L13.52|
;;;1217     } 
;;;1218   
;;;1219     /* mask all reserved bits */
;;;1220     tmpreg &= (uint32_t)RESERVED_MASK;
000034  4a06              LDR      r2,|L13.80|
000036  4010              ANDS     r0,r0,r2
;;;1221   
;;;1222     /* Check the status of the specified DMA interrupt */
;;;1223     if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
000038  4208              TST      r0,r1
00003a  d001              BEQ      |L13.64|
00003c  b103              CBZ      r3,|L13.64|
;;;1224     {
;;;1225       /* DMA_IT is set */
;;;1226       bitstatus = SET;
00003e  2401              MOVS     r4,#1
                  |L13.64|
;;;1227     }
;;;1228     else
;;;1229     {
;;;1230       /* DMA_IT is reset */
;;;1231       bitstatus = RESET;
;;;1232     }
;;;1233   
;;;1234     /* Return the DMA_IT status */
;;;1235     return  bitstatus;
000040  4620              MOV      r0,r4
;;;1236   }
000042  bd30              POP      {r4,r5,pc}
;;;1237   
                          ENDP

                  |L13.68|
                          DCD      0x40026410
                  |L13.72|
                          DCD      0x40026000
                  |L13.76|
                          DCD      0x0f3c0f3c
                  |L13.80|
                          DCD      0x0f7d0f7d

                          AREA ||i.DMA_ITConfig||, CODE, READONLY, ALIGN=1

                  DMA_ITConfig PROC
;;;1117     */
;;;1118   void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
000000  060b              LSLS     r3,r1,#24
;;;1119   {
000002  d509              BPL      |L14.24|
;;;1120     /* Check the parameters */
;;;1121     assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;1122     assert_param(IS_DMA_CONFIG_IT(DMA_IT));
;;;1123     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1124   
;;;1125     /* Check if the DMA_IT parameter contains a FIFO interrupt */
;;;1126     if ((DMA_IT & DMA_IT_FE) != 0)
;;;1127     {
;;;1128       if (NewState != DISABLE)
000004  b122              CBZ      r2,|L14.16|
;;;1129       {
;;;1130         /* Enable the selected DMA FIFO interrupts */
;;;1131         DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE;
000006  6943              LDR      r3,[r0,#0x14]
000008  f0430380          ORR      r3,r3,#0x80
00000c  6143              STR      r3,[r0,#0x14]
00000e  e003              B        |L14.24|
                  |L14.16|
;;;1132       }    
;;;1133       else 
;;;1134       {
;;;1135         /* Disable the selected DMA FIFO interrupts */
;;;1136         DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE;  
000010  6943              LDR      r3,[r0,#0x14]
000012  f0230380          BIC      r3,r3,#0x80
000016  6143              STR      r3,[r0,#0x14]
                  |L14.24|
;;;1137       }
;;;1138     }
;;;1139   
;;;1140     /* Check if the DMA_IT parameter contains a Transfer interrupt */
;;;1141     if (DMA_IT != DMA_IT_FE)
000018  2980              CMP      r1,#0x80
00001a  d005              BEQ      |L14.40|
;;;1142     {
;;;1143       if (NewState != DISABLE)
;;;1144       {
;;;1145         /* Enable the selected DMA transfer interrupts */
;;;1146         DMAy_Streamx->CR |= (uint32_t)(DMA_IT  & TRANSFER_IT_ENABLE_MASK);
00001c  f001011e          AND      r1,r1,#0x1e
000020  b11a              CBZ      r2,|L14.42|
000022  6802              LDR      r2,[r0,#0]
000024  430a              ORRS     r2,r2,r1
000026  6002              STR      r2,[r0,#0]
                  |L14.40|
;;;1147       }
;;;1148       else
;;;1149       {
;;;1150         /* Disable the selected DMA transfer interrupts */
;;;1151         DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);
;;;1152       }    
;;;1153     }
;;;1154   }
000028  4770              BX       lr
                  |L14.42|
00002a  6802              LDR      r2,[r0,#0]            ;1151
00002c  438a              BICS     r2,r2,r1              ;1151
00002e  6002              STR      r2,[r0,#0]            ;1151
000030  4770              BX       lr
;;;1155   
                          ENDP


                          AREA ||i.DMA_Init||, CODE, READONLY, ALIGN=2

                  DMA_Init PROC
;;;318      */
;;;319    void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct)
000000  b530              PUSH     {r4,r5,lr}
;;;320    {
;;;321      uint32_t tmpreg = 0;
;;;322    
;;;323      /* Check the parameters */
;;;324      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;325      assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel));
;;;326      assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR));
;;;327      assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
;;;328      assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
;;;329      assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
;;;330      assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
;;;331      assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
;;;332      assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
;;;333      assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
;;;334      assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode));
;;;335      assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold));
;;;336      assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst));
;;;337      assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst));
;;;338    
;;;339      /*------------------------- DMAy Streamx CR Configuration ------------------*/
;;;340      /* Get the DMAy_Streamx CR value */
;;;341      tmpreg = DMAy_Streamx->CR;
000002  6803              LDR      r3,[r0,#0]
;;;342    
;;;343      /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
;;;344      tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
000004  4a12              LDR      r2,|L15.80|
000006  4013              ANDS     r3,r3,r2
;;;345                             DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
;;;346                             DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
;;;347                             DMA_SxCR_DIR));
;;;348    
;;;349      /* Configure DMAy Streamx: */
;;;350      /* Set CHSEL bits according to DMA_CHSEL value */
;;;351      /* Set DIR bits according to DMA_DIR value */
;;;352      /* Set PINC bit according to DMA_PeripheralInc value */
;;;353      /* Set MINC bit according to DMA_MemoryInc value */
;;;354      /* Set PSIZE bits according to DMA_PeripheralDataSize value */
;;;355      /* Set MSIZE bits according to DMA_MemoryDataSize value */
;;;356      /* Set CIRC bit according to DMA_Mode value */
;;;357      /* Set PL bits according to DMA_Priority value */
;;;358      /* Set MBURST bits according to DMA_MemoryBurst value */
;;;359      /* Set PBURST bits according to DMA_PeripheralBurst value */
;;;360      tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR |
000008  68cc              LDR      r4,[r1,#0xc]
00000a  680a              LDR      r2,[r1,#0]
00000c  4322              ORRS     r2,r2,r4
00000e  e9d14505          LDRD     r4,r5,[r1,#0x14]
000012  432c              ORRS     r4,r4,r5
000014  4322              ORRS     r2,r2,r4
000016  69cc              LDR      r4,[r1,#0x1c]
000018  4322              ORRS     r2,r2,r4
00001a  6a0c              LDR      r4,[r1,#0x20]
00001c  4322              ORRS     r2,r2,r4
00001e  6a4c              LDR      r4,[r1,#0x24]
000020  4322              ORRS     r2,r2,r4
000022  6a8c              LDR      r4,[r1,#0x28]
000024  4322              ORRS     r2,r2,r4
000026  6b4c              LDR      r4,[r1,#0x34]
000028  4322              ORRS     r2,r2,r4
00002a  6b8c              LDR      r4,[r1,#0x38]
00002c  4322              ORRS     r2,r2,r4
00002e  431a              ORRS     r2,r2,r3
;;;361                DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
;;;362                DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
;;;363                DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority |
;;;364                DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst;
;;;365    
;;;366      /* Write to DMAy Streamx CR register */
;;;367      DMAy_Streamx->CR = tmpreg;
000030  6002              STR      r2,[r0,#0]
;;;368    
;;;369      /*------------------------- DMAy Streamx FCR Configuration -----------------*/
;;;370      /* Get the DMAy_Streamx FCR value */
;;;371      tmpreg = DMAy_Streamx->FCR;
000032  6942              LDR      r2,[r0,#0x14]
;;;372    
;;;373      /* Clear DMDIS and FTH bits */
;;;374      tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
000034  f0220307          BIC      r3,r2,#7
;;;375    
;;;376      /* Configure DMAy Streamx FIFO: 
;;;377        Set DMDIS bits according to DMA_FIFOMode value 
;;;378        Set FTH bits according to DMA_FIFOThreshold value */
;;;379      tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold;
000038  e9d1240b          LDRD     r2,r4,[r1,#0x2c]
00003c  4322              ORRS     r2,r2,r4
00003e  431a              ORRS     r2,r2,r3
;;;380    
;;;381      /* Write to DMAy Streamx CR */
;;;382      DMAy_Streamx->FCR = tmpreg;
000040  6142              STR      r2,[r0,#0x14]
;;;383    
;;;384      /*------------------------- DMAy Streamx NDTR Configuration ----------------*/
;;;385      /* Write to DMAy Streamx NDTR register */
;;;386      DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize;
000042  690a              LDR      r2,[r1,#0x10]
000044  6042              STR      r2,[r0,#4]
;;;387    
;;;388      /*------------------------- DMAy Streamx PAR Configuration -----------------*/
;;;389      /* Write to DMAy Streamx PAR */
;;;390      DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
000046  684a              LDR      r2,[r1,#4]
000048  6082              STR      r2,[r0,#8]
;;;391    
;;;392      /*------------------------- DMAy Streamx M0AR Configuration ----------------*/
;;;393      /* Write to DMAy Streamx M0AR */
;;;394      DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr;
00004a  6889              LDR      r1,[r1,#8]
00004c  60c1              STR      r1,[r0,#0xc]
;;;395    }
00004e  bd30              POP      {r4,r5,pc}
;;;396    
                          ENDP

                  |L15.80|
                          DCD      0xf01c803f

                          AREA ||i.DMA_MemoryTargetConfig||, CODE, READONLY, ALIGN=1

                  DMA_MemoryTargetConfig PROC
;;;801      */
;;;802    void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
000000  2a00              CMP      r2,#0
;;;803                               uint32_t DMA_MemoryTarget)
;;;804    {
000002  d001              BEQ      |L16.8|
;;;805      /* Check the parameters */
;;;806      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;807      assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget));
;;;808        
;;;809      /* Check the Memory target to be configured */
;;;810      if (DMA_MemoryTarget != DMA_Memory_0)
;;;811      {
;;;812        /* Write to DMAy Streamx M1AR */
;;;813        DMAy_Streamx->M1AR = MemoryBaseAddr;    
000004  6101              STR      r1,[r0,#0x10]
;;;814      }  
;;;815      else
;;;816      {
;;;817        /* Write to DMAy Streamx M0AR */
;;;818        DMAy_Streamx->M0AR = MemoryBaseAddr;  
;;;819      }
;;;820    }
000006  4770              BX       lr
                  |L16.8|
000008  60c1              STR      r1,[r0,#0xc]          ;818
00000a  4770              BX       lr
;;;821    
                          ENDP


                          AREA ||i.DMA_PeriphIncOffsetSizeConfig||, CODE, READONLY, ALIGN=1

                  DMA_PeriphIncOffsetSizeConfig PROC
;;;513      */
;;;514    void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos)
000000  2900              CMP      r1,#0
;;;515    {
000002  d004              BEQ      |L17.14|
;;;516      /* Check the parameters */
;;;517      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;518      assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos));
;;;519    
;;;520      /* Check the needed Peripheral increment offset */
;;;521      if(DMA_Pincos != DMA_PINCOS_Psize)
;;;522      {
;;;523        /* Configure DMA_SxCR_PINCOS bit with the input parameter */
;;;524        DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS;     
000004  6801              LDR      r1,[r0,#0]
000006  f4414100          ORR      r1,r1,#0x8000
00000a  6001              STR      r1,[r0,#0]
;;;525      }
;;;526      else
;;;527      {
;;;528        /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */
;;;529        DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS;    
;;;530      }
;;;531    }
00000c  4770              BX       lr
                  |L17.14|
00000e  6801              LDR      r1,[r0,#0]            ;529
000010  f4214100          BIC      r1,r1,#0x8000         ;529
000014  6001              STR      r1,[r0,#0]            ;529
000016  4770              BX       lr
;;;532    
                          ENDP


                          AREA ||i.DMA_SetCurrDataCounter||, CODE, READONLY, ALIGN=1

                  DMA_SetCurrDataCounter PROC
;;;631      */
;;;632    void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter)
000000  6041              STR      r1,[r0,#4]
;;;633    {
;;;634      /* Check the parameters */
;;;635      assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
;;;636    
;;;637      /* Write the number of data units to be transferred */
;;;638      DMAy_Streamx->NDTR = (uint16_t)Counter;
;;;639    }
000002  4770              BX       lr
;;;640    
                          ENDP


                          AREA ||i.DMA_StructInit||, CODE, READONLY, ALIGN=1

                  DMA_StructInit PROC
;;;402      */
;;;403    void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
000000  2100              MOVS     r1,#0
;;;404    {
;;;405      /*-------------- Reset DMA init structure parameters values ----------------*/
;;;406      /* Initialize the DMA_Channel member */
;;;407      DMA_InitStruct->DMA_Channel = 0;
000002  6001              STR      r1,[r0,#0]
;;;408    
;;;409      /* Initialize the DMA_PeripheralBaseAddr member */
;;;410      DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
000004  6041              STR      r1,[r0,#4]
;;;411    
;;;412      /* Initialize the DMA_Memory0BaseAddr member */
;;;413      DMA_InitStruct->DMA_Memory0BaseAddr = 0;
000006  6081              STR      r1,[r0,#8]
;;;414    
;;;415      /* Initialize the DMA_DIR member */
;;;416      DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory;
000008  60c1              STR      r1,[r0,#0xc]
;;;417    
;;;418      /* Initialize the DMA_BufferSize member */
;;;419      DMA_InitStruct->DMA_BufferSize = 0;
00000a  6101              STR      r1,[r0,#0x10]
;;;420    
;;;421      /* Initialize the DMA_PeripheralInc member */
;;;422      DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00000c  6141              STR      r1,[r0,#0x14]
;;;423    
;;;424      /* Initialize the DMA_MemoryInc member */
;;;425      DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
00000e  6181              STR      r1,[r0,#0x18]
;;;426    
;;;427      /* Initialize the DMA_PeripheralDataSize member */
;;;428      DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
000010  61c1              STR      r1,[r0,#0x1c]
;;;429    
;;;430      /* Initialize the DMA_MemoryDataSize member */
;;;431      DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
000012  6201              STR      r1,[r0,#0x20]
;;;432    
;;;433      /* Initialize the DMA_Mode member */
;;;434      DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
000014  6241              STR      r1,[r0,#0x24]
;;;435    
;;;436      /* Initialize the DMA_Priority member */
;;;437      DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
000016  6281              STR      r1,[r0,#0x28]
;;;438    
;;;439      /* Initialize the DMA_FIFOMode member */
;;;440      DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable;
000018  62c1              STR      r1,[r0,#0x2c]
;;;441    
;;;442      /* Initialize the DMA_FIFOThreshold member */
;;;443      DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
00001a  6301              STR      r1,[r0,#0x30]
;;;444    
;;;445      /* Initialize the DMA_MemoryBurst member */
;;;446      DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single;
00001c  6341              STR      r1,[r0,#0x34]
;;;447    
;;;448      /* Initialize the DMA_PeripheralBurst member */
;;;449      DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
00001e  6381              STR      r1,[r0,#0x38]
;;;450    }
000020  4770              BX       lr
;;;451    
                          ENDP


;*** Start embedded assembler ***

#line 1 "..\\..\\Libraries\\STM32F4xx_StdPeriph_Driver\\src\\stm32f4xx_dma.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f4xx_dma_c_e9b554c0____REV16|
#line 129 "..\\..\\Libraries\\CMSIS\\Include\\core_cmInstr.h"
|__asm___15_stm32f4xx_dma_c_e9b554c0____REV16| PROC
#line 130

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f4xx_dma_c_e9b554c0____REVSH|
#line 144
|__asm___15_stm32f4xx_dma_c_e9b554c0____REVSH| PROC
#line 145

 revsh r0, r0
 bx lr
	ENDP
	AREA ||.rrx_text||, CODE
	THUMB
	EXPORT |__asm___15_stm32f4xx_dma_c_e9b554c0____RRX|
#line 300
|__asm___15_stm32f4xx_dma_c_e9b554c0____RRX| PROC
#line 301

 rrx r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***