cpu_bsp.txt
5.06 KB
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; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\flash\obj\cpu_bsp.o --asm_dir=.\Flash\List\ --list_dir=.\Flash\List\ --depend=.\flash\obj\cpu_bsp.d --cpu=Cortex-M4.fp --apcs=interwork -O1 --diag_suppress=9931,870 -I..\..\Libraries\CMSIS\Include -I..\..\Libraries\CMSIS\Device\ST\STM32F4xx\Include -I..\..\Libraries\STM32F4xx_StdPeriph_Driver\inc -I..\..\uCOS-III\uC-CPU -I..\..\uCOS-III\uC-LIB -I..\..\uCOS-III\uCOS-III\Ports -I..\..\uCOS-III\uCOS-III\Source -I..\..\uCOS-III\uC-CPU\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uC-LIB\Ports\ARM-Cortex-M4\RealView -I..\..\uCOS-III\uCOS-III\Ports\ARM-Cortex-M4\Generic\RealView -I..\..\User -I..\..\User\bsp -I..\..\User\bsp\inc -I..\..\User\libapp -I..\..\RL-ARM\Config -I..\..\RL-ARM\Driver -I..\..\RL-ARM\RL-RTX\inc -I..\..\User\bsp\BSP -I..\..\RL-ARM\RL-CAN -I..\..\Libraries\DSP_LIB\Include -I..\..\MODBUS\modbus\rtu -I..\..\MODBUS\BARE\port -I..\..\MODBUS\modbus\include -I..\..\User\bsp\BSP -I..\..\PLC -I..\..\Avoid -I..\..\User\parameter -I..\..\User\LaserMotionCtr -I..\..\User\W5100S -I..\..\User\bsp -I..\..\User\CHASSIS -I..\..\User\CONTROLFUNCTION -I..\..\User\DATAUPDATE -I..\..\User\HARAWARE -I..\..\User\MOTORDRIVER -I..\..\User\NAVAGATION -I..\..\User\PLATFORM -I..\..\User\SENSOR -I.\RTE\_Flash -IC:\Users\YDJ\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include -IC:\Users\YDJ\AppData\Local\Arm\Packs\Keil\STM32F4xx_DFP\2.13.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include -D__UVISION_VERSION=527 -D_RTE_ -DSTM32F407xx -DUSE_STDPERIPH_DRIVER -DSTM32F40_41xxx -D__RTX -D__FPU_USED=1 --omf_browse=.\flash\obj\cpu_bsp.crf ..\..\User\cpu_bsp.c]
THUMB
AREA ||i.CPU_TS32_to_uSec||, CODE, READONLY, ALIGN=2
CPU_TS32_to_uSec PROC
;;;346 #if (CPU_CFG_TS_32_EN == DEF_ENABLED)
;;;347 CPU_INT64U CPU_TS32_to_uSec (CPU_TS32 ts_cnts)
000000 b510 PUSH {r4,lr}
;;;348 {
000002 4604 MOV r4,r0
;;;349 CPU_INT64U ts_us;
;;;350 CPU_INT64U fclk_freq;
;;;351
;;;352 fclk_freq = BSP_CPU_ClkFreq();
000004 f7fffffe BL BSP_CPU_ClkFreq
000008 2100 MOVS r1,#0
;;;353 ts_us = ts_cnts / (fclk_freq / DEF_TIME_NBR_uS_PER_SEC);
00000a 4a05 LDR r2,|L1.32|
00000c 2300 MOVS r3,#0
00000e f7fffffe BL __aeabi_uldivmod
000012 4602 MOV r2,r0
000014 460b MOV r3,r1
000016 4620 MOV r0,r4
000018 2100 MOVS r1,#0
00001a f7fffffe BL __aeabi_uldivmod
;;;354
;;;355 return (ts_us);
;;;356 }
00001e bd10 POP {r4,pc}
;;;357 #endif
ENDP
|L1.32|
DCD 0x000f4240
AREA ||i.CPU_TS_TmrInit||, CODE, READONLY, ALIGN=2
CPU_TS_TmrInit PROC
;;;179 #if (CPU_CFG_TS_TMR_EN == DEF_ENABLED)
;;;180 void CPU_TS_TmrInit (void)
000000 b510 PUSH {r4,lr}
;;;181 {
;;;182 CPU_INT32U fclk_freq;
;;;183
;;;184
;;;185 fclk_freq = BSP_CPU_ClkFreq();
000002 f7fffffe BL BSP_CPU_ClkFreq
;;;186
;;;187 CPU_REG_DEM_CR |= (CPU_INT32U)CPU_BIT_DEM_CR_TRCENA; /* Enable Cortex-M4's DWT CYCCNT reg. */
000006 4908 LDR r1,|L2.40|
000008 680a LDR r2,[r1,#0]
00000a f0427280 ORR r2,r2,#0x1000000
00000e 600a STR r2,[r1,#0]
;;;188 CPU_REG_DWT_CYCCNT = (CPU_INT32U)0u;
000010 4906 LDR r1,|L2.44|
000012 2200 MOVS r2,#0
000014 604a STR r2,[r1,#4]
;;;189 CPU_REG_DWT_CR |= (CPU_INT32U)CPU_BIT_DWT_CR_CYCCNTENA;
000016 680a LDR r2,[r1,#0]
000018 f0420201 ORR r2,r2,#1
00001c 600a STR r2,[r1,#0]
;;;190
;;;191 CPU_TS_TmrFreqSet((CPU_TS_TMR_FREQ)fclk_freq);
00001e e8bd4010 POP {r4,lr}
000022 f7ffbffe B.W CPU_TS_TmrFreqSet
;;;192 }
;;;193 #endif
ENDP
000026 0000 DCW 0x0000
|L2.40|
DCD 0xe000edfc
|L2.44|
DCD 0xe0001000
AREA ||i.CPU_TS_TmrRd||, CODE, READONLY, ALIGN=2
CPU_TS_TmrRd PROC
;;;278 #if (CPU_CFG_TS_TMR_EN == DEF_ENABLED)
;;;279 CPU_TS_TMR CPU_TS_TmrRd (void)
000000 4801 LDR r0,|L3.8|
;;;280 {
;;;281 CPU_TS_TMR ts_tmr_cnts;
;;;282
;;;283 ts_tmr_cnts = (CPU_TS_TMR)CPU_REG_DWT_CYCCNT;
000002 6840 LDR r0,[r0,#4]
;;;284
;;;285 return (ts_tmr_cnts);
;;;286 }
000004 4770 BX lr
;;;287 #endif
ENDP
000006 0000 DCW 0x0000
|L3.8|
DCD 0xe0001000